Latest threads in Field-Programmable Gate Arrays

Functional problems with Stratix II when configuring at higher temperatures?

Hello, in my project I have 20 boards with an Altera Stratix II EP2S60 FPGA. When configuring and operating at room tem...

0 20yrs

henn2005

0 20yrs henn2005

Oh no! Resets Again? Yes, but it could be important.

Important if you need your designs to cleanly reset every time. Apologies, but many folks are still posting code for as...

20 20yrs

john.l.smith

20 20yrs john.l.smith

Help Needed Regarding VPR

Hi, We need to evaluate new CLB architectures for routing area and delay. In VPR how can I specify my CLB architecture...

1 20yrs

vivekgarg330

1 20yrs vivekgarg330

Chipscope Pro License Problem

Has anyone had any problems with Chipscope Pro licenses? I evaluated Chipscope Pro a couple months ago and got my compa...

1 20yrs

sharpa17

1 20yrs sharpa17

Virtex 4 FIFO16 blocks - Corruption ?

Hi, We're faced with a strange problem ... While investigating a bug in one design, we could only observe that behavior...

8 20yrs

com.246tNt

8 20yrs com.246tNt

Xilinx routing details

Is there a description of some type on Xilinx' routing resources within its FPGA's? I am currently using a Spartan3 but...

1 20yrs

tlassiter

1 20yrs tlassiter

Bidirectional bus control

Hi, I am designing a peripheral interface IO chip that implements a bidirectional bus with a microprocessor. The proble...

2 20yrs

cvdagli

2 20yrs cvdagli

synthesis

Hi. i wanted a help from this group.i'am currently working on synthesis and need some articles or material how to proce...

5 20yrs

abrar_ahmed_313

5 20yrs abrar_ahmed_313

hi everyone, tell me something about Cyclone II.

hi, i'm grant, studying computer engineering in university of ottawa i'm using altera cyclone II on up3 board with quar...

7 20yrs

badgrant

7 20yrs badgrant

FPGA Reconfiguration : Virtex-4 Frames

Hello everybody, I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Familie...

4 20yrs

Andreas_Nett

4 20yrs Andreas_Nett

Setting the environment variable in ISE 7.1?

How does one set the environmental variable in ISE 7.1? The following error message was obtained: ERROR:Place:645 - A c...

6 20yrs

xyz.interactive

6 20yrs xyz.interactive

Parallel Cable IV not detecting

simple question... IMPACT doesn't recognize my xilinx parallel cable IV when downloading projects to the board. I have...

5 20yrs

aj.bohra

5 20yrs aj.bohra

aliases

hi , when i synthesize using xst i get aliases for certain nets what are these and why they appear.

0 20yrs

balaji286

0 20yrs balaji286

Xilinx clock IOB Place Error 645

I am getting this error. ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The c...

2 20yrs

bradsmallridge

2 20yrs bradsmallridge

FPGA CAM/TCAM

It looks like Altera's Flex20 is the only FPGA with build in support for instantiate high density CAM/TCAM. The Xilinx...

1 20yrs

tony.p.lee

1 20yrs tony.p.lee

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