hi,
I made a programe for block matching motion estimation.In this i hav
to compare the (4*4) matrics of current frame,with 18,(4*4) mtrics o search frame.each element of matrics is pixel value(containing bit).In first clock cycle (1,1) element of all the matrics is goin to the 19 inputs of the programe.In next clock cycle(1,2) elements o all matrics will be on the inputs.Their is 18 processing elemen inside the programe,each processing element getting one input fro search frame and one input from data frame.data frame input is commo in all processing element.
so i have to give 18(search frame pixel)+1 data frame pixel in ever
clock cycle in my verilog programe.
now for implementing this in FPGA,i m using sparta3xp200ft256,that i
having 100 I/O pin,but i require more input pin. please suggest any method to reduce input pin,so that i can check i in spartan kit. How can i give test signal to spartan signal for this by using xilin webpack7.1