Bidirectional Bus

Nov 23, 2005 2 Replies
Z

H I want to correlate my question to Chintan's problem and Alex answer I usually use the method suggested by Alex to handle a bidirectiona bus, but post PAR simulation (using modelsim) shows the signals o the bus delayed of about 12 ns and undefined for the next 5-6 n before to begin stable. When bus comes back in Z state there's als a period of instability of 5-6 ns.



The bus default state is 'Z'. It changes state during writing an



readind operation. Microprocessor interface operations use a clock of 80Mhz, but writn operation from FPGA to Micro is asynchornous.



I have also noted that this time of instability decreases (to 2-3 ns



when I do PAR whit High Effort Level.



Is this a normal situation? or It should be better to investigate fo



the origin of the instability



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D

I am assuming that by "instability", you mean that the bus is rapidly changing between a bunch of different values. If so, the origin of the "instability" is variation in the times that the various bits take to get to the output pins. If you are not using registered outputs, then this is normal.

In general, there are two approaches that you can use. One is to apply a timing constraint, something like: TIMESPEC "TSCLK2PADS" = FROM "FFS" TO "PADS" 12 ns; That should restrict the period of instability, assuming the tool is capable of meeting the timing.

The other solution is to register the outputs. Something like: MICROPROCESSOR_D_BUS

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Z

Hi! Duane Thanks a lot for your answer With "instability I mean that modelsim indicate buffer with re transition (undefined) before that normal transition begins, as yo explained I also doesn't understand the exaggerated delay (about 12-15 ns) tha signals have before to change state, this delay doesn't depend on th system frequency because output isn't registered. Thans ... bye

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