H I want to correlate my question to Chintan's problem and Alex answer I usually use the method suggested by Alex to handle a bidirectiona bus, but post PAR simulation (using modelsim) shows the signals o the bus delayed of about 12 ns and undefined for the next 5-6 n before to begin stable. When bus comes back in Z state there's als a period of instability of 5-6 ns.
The bus default state is 'Z'. It changes state during writing an
readind operation. Microprocessor interface operations use a clock of 80Mhz, but writn operation from FPGA to Micro is asynchornous.
I have also noted that this time of instability decreases (to 2-3 ns
when I do PAR whit High Effort Level.
Is this a normal situation? or It should be better to investigate fo
the origin of the instability