Case expression?

You either wait for the next rev of VHDL (and then wait a couple of years for the tools to catch up), or you use a temporary variable. I don't know of any other way.

tmp := bit1 & bit2 & bit3; case tmp is when ...

BTW, you shouldn't have parentheses around the case expression.

Regards, Allan

Another way would be to use Verilog.

Many thanks.

I've used a temporary variable but it's not so readable. Shame really to have to do it.

Unfortunately in the UK you're more employable if you know VHDL. I have written in Verilog and quite like the C type structure. Since I'd like to pay my bills I feel tied to VHDL.

You're even more employable if you have a strong knowedge of both.

Regards, Allan

... and even more employable if you can spell.

Even more more so it can see your own mistakes before anyone else!

case SLV3'(bit1 & bit2 & bit3) is

where SLV3 is

subtype SLV3 is std_logic_vector(2 downto 0);

or just put in the full subtype expression instead of SLV3 if you want to.

HTH

Rick

Probably the nicest way is to declare a subtype - you can do this locally in the process, so it doesn't pollute the architecture. Then type-qualify the expression:

process (...) [other declarations] subtype SLV3 is std_logic_vector(2 downto 0); begin ... CASE SLV3'(bit1 & bit2 & bit3) IS ...

Note the apostrophe between subtype name and opening parenthesis.

Depending on the application, you may be able to think of a more apt name for the subtype.

HTH

Nope, then they think you are over qualifed for the job :)

-jg

Jonathan Bromley a =E9crit : [=2E..]

Be *very* careful when you use type-qualified expressions. Indeed, the expression type must be the same as the type name. If this is not the case (like here), a fully vhdl LRM compliant simulator should detect an error here.

Therefore, you'd better to use a type conversion: SLV3 (bit1 & bit2 & bit3)

JD.

Can you explain? I can't see why a concatenation of three std_logic is incompatible with my definition of SLV3.

Of course you are correct that the expression must admit of interpretation as the qualifying type, but in this case I think it's OK. I'm happy to be proved wrong if you can cite the appropriate bit of the LRM, though.

Jonathan Bromley a =E9crit :

This problem has been discussed in:

See LCS2 (page 5).

Basically, subtype of (bit1 & bit2 & bit3) is std_logic_vector (0 to

JD.