Be *very* careful when you use type-qualified expressions. Indeed, the expression type must be the same as the type name. If this is not the case (like here), a fully vhdl LRM compliant simulator should detect an error here.
Therefore, you'd better to use a type conversion: SLV3 (bit1 & bit2 & bit3)
Can you explain? I can't see why a concatenation of three std_logic is incompatible with my definition of SLV3.
Of course you are correct that the expression must admit of interpretation as the qualifying type, but in this case I think it's OK. I'm happy to be proved wrong if you can cite the appropriate bit of the LRM, though.
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how