Hi!,
I am a new pg student working on parallelism and FPGA programming. My interest is working at the highest level possible, at algorithmic and system level. I have been looking at libraries as JHDL and SustemC, and languages as Handel-C and Verilog. I am involved in a research project for developing IP core using a hardware/software approach (co-design and co-simulation). Because I must start as soon a s possible and want to use the latest about techniques, methods, methodologies and technology I need someone helps giving some information about the following:
- What Is Runtime reconfiguration, partial reconfiguration or dynamic reconfiguration?. 2. How Does dynamic reconfiguration works at hardware and software level? 3. To take advantage of dynamic reconfiguration Do I need the software tool or fpga board supports dynamic reconfigration?. 4. Is it possible to exploit dynamic reconfiguration at high level Programming level ? I mean, Can programmer users do this? 5. Does SystemC support dynamic reconfiguration? and Handel-C? Can I develop applications using rutime reconfiguration with SystemC?
- May someone recommend me any FPGA Board from Xilinx, Altera or Celoxica supports runtime reconfiguration? 7. What about any FPGA Development Kit supports runtime reconfiguration based on C/C++?
I thank if you can help explaining me all about this or giving me documents or links to find this. I trust your advice. I am sorry for the troubles in advance.
Thanks a lot. Carlos