Latest threads in Field-Programmable Gate Arrays

HDL Chip Design

I am looking to buy either a new or used copy of the HDL Chip Design book by Douglas Smith. Email me if you have a copy...

1 20yrs

tori_a9

1 20yrs tori_a9

instruction counts and cache hits/misses on FPGA

HI group, I am searching for some technique which can give me instruction count and cache hits/misses for a configurati...

5 20yrs

pankajgode

5 20yrs pankajgode

Altera Pin not used in Quartus project but drives logic

Hello all, Environment FPGA : Altera Cyclone FPGA(EP1c20F324I7) Synthesis Tool : Quartus Integrated Synthesis(Quartus V...

2 20yrs

monica_dsz

2 20yrs monica_dsz

AD9218, what will the negative values be in binary mode?

When my DAC output is from 0-1V, and is fed into 10-bit AD9218 which is set to binary mode, what binary value will I get...

6 20yrs

Francis.invalid

6 20yrs Francis.invalid

ADC keeps outputting negative numbers, how?

I have some digital waveforms, during the idle interval, it's zero, while in active mode, some patterns are output. Thi...

3 20yrs

Francis.invalid

3 20yrs Francis.invalid

boot from flah

Hi all, I am doing some experiments with virtex-ii pro50 fpga baord. I want to put my programme in the flash, and make...

5 20yrs

lnzhao

5 20yrs lnzhao

async fifo design

Hi, I'm designing an "On Chip Network" System consisting of one network master and several network interfaces. Every in...

9 20yrs

michaeldre

9 20yrs michaeldre

Virtex 4 Configuration

hello have a few questions regarding the configuration pins on the V4 chip 1. in the Virtex-4 Configuration Guide [ug07...

3 20yrs

talon

3 20yrs talon

VLSI Processor Cores

Hi All I want to Research in the "Processors Core Development" , can any one suggest me of any current topics to conduc...

1 20yrs

abhishekbedi

1 20yrs abhishekbedi

Virtex 4 Tapped Delay Lines

Hi I was wondering if anybody could help. I'm looking for a way t create tapped delay lines on a Xilinx Virtex 4 withou...

19 20yrs

alastairlynch

19 20yrs alastairlynch

Xilinx timing constraint question

I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm seeing the following unconstrained path in the timin...

4 20yrs

johnp3+nospam

4 20yrs johnp3+nospam

Distributed RAMs / SRL: Why not, Altera?

Hello, currently we are working on relatively large project with a focus on signal processing algorithms. Some months a...

8 20yrs

michikramer

8 20yrs michikramer

RocketChips?

Hey Xilinx, before you bought RocketChips you should have checked their company website better. They had some photos of...

0 20yrs

altera_smells

0 20yrs altera_smells

virtex 4 extreme DSP linux PCI driver

i recently bought the v4 extreme DSP development kit and am trying to get a linux PCI device driver for it. up till now...

0 20yrs

wallge

0 20yrs wallge

LF: XC4VFX20 samples

Hi folks, We have laid out a board for XC4VFX20-10FF672, but can't get a single sample. The local distributors have bee...

2 20yrs

mbmsv

2 20yrs mbmsv

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