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Virtex 4 Configuration

hello have a few questions regarding the configuration pins on the V4 chip

  1. in the Virtex-4 Configuration Guide [ug071].pdf, pg 35 figure 2-12, Note
1

  1. The DONE pin is by default an open-drain output requiring an external pull-up

resistor. A 330? pull-up resistor is recommended. In this arrangement, the active

DONE driver can be enabled, eliminating the need for an external pull-up resistor.

not sure what this means can the DONE configuration pin be driver enabled? can the other pins also be enabled or pulled up or pulled down? or if the fpga has some spare pins, and pulling up or pulling down the spare pin, then wire it to any of the configuration pins, would that not work like an external pulled up/down resistor?

lastly if any of the above is possible can the same pin be both pulled up and pulled down, then wired to CCLK, it might take care of Note 10

  1. The CCLK net requires Thevenin parallel termination.

thanks

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Reply to
Enzo Guerra
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There can be a problem, when DONE is released by the FPGA, if its risetime is too slow. From what I understand, this is only a problem if there are more than one FPGA's DONE pins tied together.

If the open-drain configuration is used, and there are several DONE pins in parallel, then the rise time can be minimized by using a small-valued pullup resistor (330 is the minimum value, IIRC).

If there is only one FPGA being configured (i.e., the DONE pins are not paralleled with others), then the DONE pin can be configured to have a totem pole output stage (push-pull). This is a bitgen option (IIRC). You don't want to use this option if you have more than one DONE in parallel since you will (eventually) have one DONE pulling low and another pulling high.

See above.

Sure, but (generally) only after the user I/O has been configured. See below.

Remember, this is all happening 'pre-configuration'. The user I/O pins are not active, at this time. There is a mode pin option to allow the pre-configured user I/O to have pullups (during configuration), but connecting a bunch of user I/O to the DONE pin, for the sake of using the additional I/O pullup current, is silly. Just add a resistor. They're cheap and small.

The CCLK pin a clock. It's critical that its signal integrity be carefully controlled -- as any other clock signal needs to be. Double clocking could result. Proper termination is a must. Start reading about "signal integrity" and "termination techniques".

Yahvelcome.

Reply to
Bob

Who/what gets confused if DONE rises slowly? Slow relative to what?

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Reply to
Hal Murray

Hal,

DONE, after it's been released, becomes an input. An option in the bitstream (via bitgen) can be setup so it looks to see if DONE's being held low, after configuration, and if so, holds off the activation of its guts. I believe that the reason for this is if there are other devices that are being configured, and their DONE pins are tied together, that activation waits until the last device has been configured before they start running.

The slowness of the risetime somehow affects a device's ability to sense the release of DONE. This is what I was told. The effect is (at least what we saw when we experienced this problem) that the device never starts up. Both solutions worked, for us -- the stronger pullup worked and and the push/pull option worked. We use the push/pull option, now, since we never tie DONE pins together.

I'm not a Xilinx employee, and I don't play one on tv, so if you're really interested I'm sure that there is some documentation on their website. Where are Peter/Austin when you need them? They've probably made so much damn money that they only, now, answer the easy questions. Ingrates!

Bob

Reply to
Bob

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