Field-Programmable Gate Arrays

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Bit-serial arithmetic on Spartan II

[Please do not mail me a copy of your followup] Having googled around, I see that there are a number of papers (and eve...
0 comments posted 20yrs
posted by legalize+jeeves
0 comments posted 20yrs posted by legalize+jeeves

nallatech benone fpga board

has anyone used this board, what do you think of it? does anyone have a linux driver for it? a schematic? thanks
1 comments posted 20yrs
posted by wallge
1 comments posted 20yrs posted by wallge

Successful use of MGT on Virtex 4

Has anyone been able to successfully simulate a test of the MGT on the Virtex-4? I've been trying to instantiate the GT...
5 comments posted 20yrs
posted by jpnguyenk
5 comments posted 20yrs posted by jpnguyenk

grabbing PCI signals, rev-eng dev board

im trying to reverse engineer a windows driver for a PCI fpga development board so i can use it on a linux machine (wri...
4 comments posted 20yrs
posted by wallge
4 comments posted 20yrs posted by wallge

first time managing a project

Hi, I just got chosen as 'project manager' for our next project. It seems like most people feel 'sorry' for me around h...
10 comments posted 20yrs
posted by gretzteam
10 comments posted 20yrs posted by gretzteam

ISE question on whats a "X_LUT3"?

Have a problem so tracing signals. What's a X_LUT3? A standard LUT3 only has an INIT value of 0 to 7. This is the "...t...
2 comments posted 20yrs
posted by fred
2 comments posted 20yrs posted by fred

Cypress FX2 bandwidth problem

We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control an...
16 comments posted 20yrs
posted by damir.makni
16 comments posted 20yrs posted by damir.makni

Slow FIFO using external SRAM

I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external single-port SRAM connected to the FPGA (Spartan...
10 comments posted 20yrs
posted by damir.makni
10 comments posted 20yrs posted by damir.makni

Merging the ML403 refence design and the GSRD design

Hello, As I would like the Ethernet performance from the GSRD design in the ML403 reference design, I would like to mer...
2 comments posted 20yrs
posted by electronics_designer
2 comments posted 20yrs posted by electronics_designer

Looking for manual for logic analyzer module 16750A.

The machine is 16702B Logic analyzer, but the module inside is 16750A 400MHz State 2GHz Timing zoom 4MSa Analyzer. I am...
4 comments posted 20yrs
posted by Francis.invalid
4 comments posted 20yrs posted by Francis.invalid

DCM Wizard

I have a design that synthesizes to run at a little over 200 MHz. I want to make the design run at 200 MHz on the Spart...
2 comments posted 20yrs
posted by ramya.sriragh
2 comments posted 20yrs posted by ramya.sriragh

Why does two channels of ADC give different outputs?

I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). When I connect I channel from DAC to I & Q ch...
16 comments posted 20yrs
posted by Francis.invalid
16 comments posted 20yrs posted by Francis.invalid

Xilinx 'unconstrained period' problem

I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm seeing the following unconstrained path in the timin...
3 comments posted 20yrs
posted by johnp3+nospam
3 comments posted 20yrs posted by johnp3+nospam

ML403 GPIO Switch not present

Hi all, I just bought an ML403 board (more precisely I bought the PowerPC and MicroBlaze Development Kit) but the 8 GPI...
1 comments posted 20yrs
posted by taileb.mehdi
1 comments posted 20yrs posted by taileb.mehdi