Q-bus or Unibus bus transactions in FPGA?

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Has anyone implemented a Q-bus or Unibus bus interface logic in an FPGA that is freely available or documented? I am interested in making a board for an LSI-11 computer that looks to the LSI-11 like a disk drive, but is really a communication circuit back to a PC that serves the drive image from a file on the PC.

Any ideas on implementation strategies would be appreciated!

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Reply to
Richard
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Not on an FPGA (PDP-11 was before their time) but the bus protocol is quite simple. Unibus has separate data and address, Q-bus has multiplexed A/D. The master sends out an address and a transfer request, and when the target is done it sends an acknowledge. It is all async, there is no bus clock.

Jon

Reply to
Jon Elson
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Jon Elson spake the secret code thusly:

Well, I didn't mean to imply that the FPGA was concurrent with the PDP-11 :-), I was more hoping that another retro computing hobbyist would have made something I could bootleg!

I suppose I'll have to do my own bus handshake implementation from the Q-bus docs (I think my processor or peripheral handbook that came with the 11/03 has one in there somewhere).

I wonder how hard it would be to get a PCB fabbed with the bus edge connector?

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Reply to
Richard

I did one in a Xilinx XC3064... many, many years ago. Unfortunately, I ditched all the documentation a few years ago... and have done a complete brain purge. Might still have the DEC documentation, though. I'll check on Wednesday.

It wasn't too hard of a bus to interface to and is quite slow.

Good luck, Ed

Reply to
GPE

Does it have the specs for the bus transcievers? I remember using some special DEC chip.

Needs gold fingers. They are big relative to modern connectors. I don't know if thats good or bad - easier to make but takes more gold.

Anybody know where to get boards with gold fingers at hobbyist prices? I keep scheming about making a few PCI cards.

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Reply to
Hal Murray

DEC did make some interface IC's for Qbus ... but *IF* I remember right... these were easily replaced with standard TTL logic.

Reply to
GPE

I did interfaces many years ago for both buses using PAL's for logic and

74F-series parts for bus drive. Probably 5V 74FCT parts would also work. If you're serious about Unibus, you'll need to know that the connector pin-out in the DEC documentation is for the bus extender cable and not where a board plugs in. A and B connectors are not used for plug-in cards, only C, D, E and F. I got a copy of the magic document from someone who got it from someone who did PC board work for DEC.

I don't have any of my documentation now except for the Unibus pinout. You'll need a copy of the board mechanicals. For Qbus there used to be prototyping breadboards available with holes on 0.1 x 0.1" centers. If you check with some hobby places like Jameco there may still be such things available if you want to breadboard your design or just lay out a "daughtercard" to wire down to the breadboard.

Good Luck, Gabor

Reply to
Gabor

There was a discussion of this on S.E.D. quite recently with one of it's denizens successfully getting a board with gold fingers fabricated at a very reasonable price.

X-Posted to s.e.d. for comments

Cheers

PeteS

Reply to
PeteS
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snipped-for-privacy@suespammers.org (Hal Murray) spake the secret code thusly:

I do recall seeing the specs for the DEC bus trainceiver chip in the handbook, yes.

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Reply to
Richard

PeteS posted:

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Richard wrote:

I designed a Q-bus interface card about 16 years ago using a CPLD for decoding logic and another CPLD for board functions -- both written in ABEL. I used DEC's ChipKit for logic buffering to the bus itself. The physical dimensions of the board fingers came from one of DEC's manuals.

Alas, it was 16 years ago and 2 companies ago, so I don't have much to offer in the way of code. But, it has been done before, so it can be done again! As for the logic interface, there are so many logic families that modern FPGA's I/O can be programmed for, I'm sure something will match the characteristics of the Q-bus (Unibus), then you don't need the ChipKit.

Cheers Tom

Reply to
tlbs

Not absolutely true, for Unibus. There were "quad" boards, and "hex" boards. Usually the hex boards just used the extra space for circuitry, and not the A&B connector pins. You have to know how the backplane section is wired, because there are a bunch of different ones for different types of interface boards.

Jon

Reply to
Jon Elson

I remember one was the SP380. One of the features is it wouldn't drag down the bus if the interface was powered down. Of course, that would break the bus grant continuity, so it was a pretty useless feature, at least for Unibus.

Jon

Reply to
Jon Elson

The AB slots at the ends of a backplane are the Unibus proper. Single-board peripherals plug into "SPC" (Small Peripheral Controller) slots which are the CDEF slots. The AB slots that are not at the ends of a backplane may be MUD (Modified Unibus Device) or Extended Unibus (22-bit addressing) slots, and should generally be avoided.

Some peripheral modules are hex size and go into an SPC slot. They plug into the AB slots, but don't use any signals from those slots (with the possible exception of power).

For the Unibus electrical spec and pinout (AB only) see the PDP-11 Unibus Design Description and the PDP-11 Bus Handbook:

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SPC and MUD generally are electrically the same as Unibus, but with different pinouts. For the pinouts you have to refer to some of the processor manuals. For instance, the SPC pinout is on page 3-8 of the PDP-11/44 User Guide, or in tabular form on page 5-26:

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That manual has the standard Unibus and MUD slot pinouts in a tabular form on page 5-25.

Extended Unibus (22-bit addressing), also known as "speical bus" is only used on a few of the AB slots of the processor backplane of the 11/24 and 11/44. I haven't seen any docs on it other than in the field maintenance print sets for those processors, and the maintenance manuals and prints for the memory that supports it (MS11-Lx, MS11-M, MS11-Px):

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Briefly, address lines A18L through A21L are present on pins BE2, BE1, AP1, and AN1 of Extended Unibus slots, but are used for other purposes on normal Unibus slots.

For the Qbus electrical specs and pinout, see the PDP-11 Bus Handbook listed above. But that doesn't cover some of the later Qbus extensions such as 22-bit addressing. For that, see Appendix F of the KDF11-B manual:

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Implementing the Qbus or Unibus protocols in an FPGA is not too difficult. More of a challenge now is implementing bus drivers and receivers that meet the electrical specifications. I've previously posted some notes on interface chips to Usenet, but I can't find it right now. My notes are at:

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Reply to
Eric Smith

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