Field-Programmable Gate Arrays

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ISE 8.1 release delayed?

ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder if it is known how much more the ISE 8.1 r...
8 comments posted 20yrs
posted by antti
8 comments posted 20yrs posted by antti

Use EMC to control a FIFO ?

Hi, all. I want to use a fifo(Xilinx IPCore) outside microblaze(of course insid the chip). Now , I use GPIO of microbla...
0 comments posted 20yrs
posted by coosign
0 comments posted 20yrs posted by coosign

Virtex-4 DSP48 placement restrictions?

Hi all, I'm looking for ideas why a design using 43 DSP48s as multipliers might not fit a V4LX25 with 48 DSPs... Sympto...
4 comments posted 20yrs
posted by brian_drummond
4 comments posted 20yrs posted by brian_drummond

Chipscope under Linux

I want to use Chipscope under Linux, but when I try to configure the connection (I have a parallel IV Cable) I get the...
1 comments posted 20yrs
posted by taileb.mehdi
1 comments posted 20yrs posted by taileb.mehdi

programming flash memeory

Hi all, Who has ever used the tool of EDK 7.1 "tools->programme flash memory" to fulfill the aim: put my file into the...
2 comments posted 20yrs
posted by lnzhao
2 comments posted 20yrs posted by lnzhao

Tip: Spotlight (OS X) indexing of VHDL files

Greetings All, For the OS X readers out there, I found this article to be very usefull for enabling Spotlight indexing...
3 comments posted 20yrs
posted by christopher.saunter
3 comments posted 20yrs posted by christopher.saunter

how to build 32X32 LUT ROM

Hi all, i got a problem in building 32X32 LUT ROM from 32X1 ROM which is there in unisim library i am not able to figur...
3 comments posted 20yrs
posted by bachimanchi
3 comments posted 20yrs posted by bachimanchi

Problem Timing Simulation CoolRunner II Design Kit

I am new to CPLD/FPGA programming. I have recently perchaged CoolRunner II EDK. I am trying to implement example VHDL T...
0 comments posted 20yrs
posted by nshrestha
0 comments posted 20yrs posted by nshrestha

Looking for FPGA Programming consultant

Hello, We have a FPGA system, listed below, and are looking for a consultant for doing development work on this system....
0 comments posted 20yrs
posted by nahum
0 comments posted 20yrs posted by nahum

Using RiscWatch with Xilinx FPGA's for powerpc

Using RiscWatch with Xilinx FPGA's for powerpc. I have Xilinx 7.1 package with xilinx fpga boards , as well ML310 with...
1 comments posted 20yrs
posted by pankajgode
1 comments posted 20yrs posted by pankajgode

Hardware Modeling Verification

Hi all, I am currently working in PCB design and layout stream. And have decided to go for Hardware Modeling Verificati...
0 comments posted 20yrs
posted by akhileshpatil
0 comments posted 20yrs posted by akhileshpatil

ML403 "small" problem

Hi all! Can some one (hopelly prom Xilinx) tell me why when I connect a monitor to ML403 Borad, the board doesn't boot...
3 comments posted 20yrs
posted by taileb.mehdi
3 comments posted 20yrs posted by taileb.mehdi

internal clock

In my chip I need seperate internal clock. can any one suggest how to implement internal clock using verilog.
1 comments posted 20yrs
posted by hirenshah.05
1 comments posted 20yrs posted by hirenshah.05