Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST

Here's a question: Are those power savings speed-agnostic, or do you also get a small improvement in speed (lower CL = Lower power ) or a small degrade in speed ( lower Drive = slower, but less power .. )

-jg

Hi Jim,

The speed vs. power trade-off is user-selectable.

The default power optimization setting in Quartus II 5.1 is "Normal compilation." On average, it achieves a dynamic power reduction of 15% vs. QII 5.0 (which did not have algorithms specifically for power optimization), and does not hurt design speed at all. This is a Stratix II result, but Cyclone II is similar. We get no speed loss because we make power optimization decisions lose to timing optimization decisions on the circuit critical path(s) in this mode.

If you want more power reduction, you can choose "Extra Effort" power optimization. On average, this achieves a dynamic power reduction of 21% vs. QII 5.0, and reduces design speed by 2%. In this mode we still try to protect the circuit critical path(s), but are not as conservative in predicting what paths might be timing critical early in the optimization flow, so sometimes we do hurt a speed-critical path.

So basically you can choose to have the algorithms be speed-agnostic (protect speed) or you can get more power reduction by allowing a small slowdown. We don't get a design speed-up vs. timing-driven compile, since timing-driven compile was already trying to minimize delay (including the capactitive load portion of delay) on the critical paths, so trying to minimize C further on areas of the circuit that are important to power ("power critical") does not help speed.

One last data point: if a design has very easy timing, we average 25% dynamic power reduction with the "Extra Effort" option, since there are no longer any timing critical paths to protect, so the whole circuit is fair game for power optimization.

Regards,

Vaughn Altera [v b e t z (at) altera.com]