Field-Programmable Gate Arrays

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FPGA : MAP slice logic into BLOCK RAM

Hi FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have wrote a VHDL code to implement shift r...
4 comments posted 20yrs
posted by pbijoy
4 comments posted 20yrs posted by pbijoy

Experiences with Actel ProAsic3E and toolchain?

I'm considering these parts for a new design, and the low static power and small footprint, instant-on features seem ni...
3 comments posted 20yrs
posted by weissber
3 comments posted 20yrs posted by weissber

Replace fast ethernet with VDSL2

Hi All, I have a embedded desig where I communicate with two boards via Fast ethernet. The design is very simple, the p...
2 comments posted 20yrs
posted by fpgakid
2 comments posted 20yrs posted by fpgakid

What graphical entry/documentation tools?

Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to c...
2 comments posted 20yrs
posted by jamesp
2 comments posted 20yrs posted by jamesp

Post PAR Simulation and Actual FPGA results differ

Hi All, I am currently developing for Xilinx SPARTAN3 FPGA. I have a design in which a FSM asserts a clock enable signa...
5 comments posted 20yrs
posted by Sudhir.Singh
5 comments posted 20yrs posted by Sudhir.Singh

2 clocks switching

Hi, in my design I would like to have the possibility to switch beetween two clock signals: 'clk' (this is my main cloc...
4 comments posted 20yrs
posted by rybol2
4 comments posted 20yrs posted by rybol2

Simulating Post-Synthesis Model on Xilinx FPGA

Hi there, I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter 6.0a simulator. The FPGA which I am down...
11 comments posted 20yrs
posted by chloe_music2003
11 comments posted 20yrs posted by chloe_music2003

Virtex 4 not meeting timing constraints

Hi, I have a design for a Virtex 4 SX35-10 that is not meeting my timing constraints. The only constraint is set in the...
4 comments posted 20yrs
posted by scottbekker
4 comments posted 20yrs posted by scottbekker

some new PCIe products

most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has already made freely available the schematic of t...
4 comments posted 20yrs
posted by antti
4 comments posted 20yrs posted by antti

PLX 9056 application

Hello, I am trying to use PLX9056 as an interface between PCI bus and local bus, in manner as simple as possible. I wou...
1 comments posted 20yrs
posted by jovajsha
1 comments posted 20yrs posted by jovajsha

Embedded ppc405 w/o RAM?

All, Is it possible to run programs on the embedded PowerPC in the Xilinx chips without external RAM and/or operating s...
8 comments posted 20yrs
posted by reidek
8 comments posted 20yrs posted by reidek

Mean value filter

Hi, 1. I want to know how to deal with marginal data for mean value filter, the pixels that cannot get full 9 neighbori...
15 comments posted 20yrs
posted by wtxwtx
15 comments posted 20yrs posted by wtxwtx

A stupid question about constraints

I have an FPGA board. I want to use ONLY one LED on the board. Is it enough to assign only one pin (the one to which is...
3 comments posted 20yrs
posted by taileb.mehdi
3 comments posted 20yrs posted by taileb.mehdi