Hi All,
I have a embedded desig where I communicate with two boards via Fast ethernet. The design is very simple, the packets are generated from a fpga and sent to the ethernet phy on MII. In the new design I'd like to replace the ethernet phy with a VSDL2 chipset, so I need only one twisted pair and for supporting more than 100 m. Has anybody did something similar? IMO it should be very straight forwarded to replace the phy with a VDSL2 chipset, but please let me know if I'm wrong.
Regards,
Kim