Hi, I know tha some EDA tools provide encryption feature to protect confidentiality of the HDL source code but how do we do this in ModelSim/FPGA Adv or in Xilinx ISE? So that I can provide an encrypted source code to someone and yet it works as real RTL desription. Please suggest. Thanks, Fahad
Securing verilog source code
Dec 09, 2005
2 Replies
Synthesise the code and send a netlist (after synthesis or P&R), use the -nodebug switch in Modelsim (receiver must use Modelsim), use an obfuscator (not that secure), translate the model into C/C++/SystemC and send the compiled code (receiver needs to use PLI/FLI/DPI etc to interface to the model), use a professional HDL->SystemC translator like Carbon (not low cost but very powerful) or set up an NDA and just send the RTL :-)
Hans
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Thanks Hans, I will try this out.
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