First IP-core designed for and tested with Spartan-3E

The IPcore is very small and actually not S3e only, but it was written because of Spartan3E, namly because S3e added the SPI loading capability and acces to all the dual purpose pins from fabric so the spi flash can be accessed after config. So thats why I wanted to have the JTAG-to-SPI bridge, it is available here

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included are sample toplevels and some short description and minimal testbench

the ipcore has been tested in Virtex4 and now thanks to

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also with Spartan-3E, but it should actually work also with cyclone and latticeEC

the core has been tested using secial custom Application that talks to the SPI over the FPGA jtag chain, but the core also allows any SVF or JAM player capable tool to be used to program the spi flash, for that purpose we have developed a very simple language standard to write down SPI programming data that embedds the programming algorithm, this in turn can be either directly executed to some JTAG cable hardware or converted to JAM/stapl or SVF, again example is in the ipcore archive. the generated SVF has been tested with real spi flash device using impact 7.1 as SVF playback engine.

Antti who is pretty happy to see something working in S3e silicon !

Reply to
Antti Lukats
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Why is a core required? Can't you just access the SPI pins directly from JTAG boundary scan? Or is this easier?

Alan Nishioka

Reply to
Alan Nishioka

sure it can be done via boundary scan, but if you need to reflash and 64mbit serial flash you can figure out how long it takes over boundary scan!

sending 111110aaaaaaaa1111

to user jtag register will be translated to single byte SPI transaction and CS pulse so there is only 1 JTAG clock per SPI byte overhead during SPI access

Antti

Reply to
Antti Lukats

That's a good point. I plan to use an SPI flash with a Spartan 3e, and I haven't quite decided how to handle the initial programming and in system programming.

Thank you for the core.

Alan Nishioka

Reply to
Alan Nishioka

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