I am working on a project that is taking a clock and inerfacing it with PLL to get a set of variable clock divisions. I am using the digilent s board as a devolopment tool, and have been getting caught up on how to us the expansion ports as generic I/O pins to output the clk signals to test I assign output and input ports to the FPGA pins that match up to th expansion port pins through the ucf. But the waveform I keep getting ou of the pins are all the same. Even the VCC and ground pins output thi bizzare waveform. Am I missing an enable pin somehwere on the board or d I need to power up the ports? Or is there another way to output test cl signals somewhere on the board? Any help would be much appreciated.
17 years ago