Hi fellow engineers,
I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some experience in board design and have already used several Virtex and Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the clock source of my Virtex-4. A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating "Clock inputs can be configured for any I/O standard, including differential I/O standards. Each clock input can be either single-ended or differential. All 16 or 32 clock inputs can be differential if desired. Global clock inputs can be configured for any I/O standard except LVDS and HT output differential standards. Only CSE output differential standards are supported by the global clock input pins." Does that mean that I am not allowed to connect an LVDS clock to the Global-clock inputs? Or did I get something wrong here? I have to use the ICS8442 because of the large frequency scale from 25-700 MHz.