Latest threads in Field-Programmable Gate Arrays

BRAM/XMD strangeness?

I have a V2P chip and am using both PPCs. Each has its own PLB bus and each PLB bus is connected to a small dual-ported...

6 20yrs

joeylrios

6 20yrs joeylrios

Xilinx HW-SPAR3_CPLD-DK kit

Please let me know any Xilinx distributor from any European Union country in order to by the HW-SPAR3_CPLD-DK kit. Xili...

1 20yrs

castel-electronics

1 20yrs castel-electronics

How to drive 4 output ports with one combinational signal

Hi, The following is the part of my code to drive 4 output ports with one combinational signal: LatchA : process(CLK66M)...

8 20yrs

wtxwtx

8 20yrs wtxwtx

ATA controller in fpga

I want to implement an ata controller in the fpga,the controller use the ultra dma mode to read and write datas,and I wa...

9 20yrs

bjzhangwn

9 20yrs bjzhangwn

NIOS II fmax on a Cyclone

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project co...

1 20yrs

alessandro.strazzero

1 20yrs alessandro.strazzero

problem with the SRAM

HI, All I have questions regarding a project i am currently working on. I have been assigned to develop an vga_controll...

1 20yrs

qingwang_1978

1 20yrs qingwang_1978

programming devices using other tools

Hi, I want to know if anybody has never programmed fpga or proms not using Impact or Quartus programmer but other (thir...

3 20yrs

bergnoli

3 20yrs bergnoli

New PCI extender

Hello everyone Just wanted to share some of my recent experience from switching to Amfeltec PCI extender from the one f...

2 20yrs

stev.lee2006

2 20yrs stev.lee2006

Mistake in Xilinx dsp-book.pdf?

Hello! While working with a MAC-FIR I came across an equation in Xilinx' DSP-book (http://www.xilinx.com/publications/b...

3 20yrs

usenet0106

3 20yrs usenet0106

Student Pricing Now on our Website

As a prelude to our new website going live there is now a webpage with outline details of our University Access Program...

3 20yrs

removethisthenleavejea

3 20yrs removethisthenleavejea

Any FPGA with programming info available?

No, I'm not talking which pins to toggle how fast and when, but is there any 600K+ gate (roughly) FPGA available which a...

4 20yrs

weingart

4 20yrs weingart

what happens in SDR-SDRAM if i exceed tRAS(max)

Hi all, There is a situtation in my controller when tRAS(max) is exceeded. My controller starts to read out from some r...

4 20yrs

subhasri.krishnan

4 20yrs subhasri.krishnan

how do I minimize the logic in this function?

I have an async function with six bits in and eight bits out (listed below). I need to minimize the logic usage (in a V...

10 20yrs

brannonking

10 20yrs brannonking

FPGA Altair Advice

I was working on a Macintosh clone project (a clone of the original 128k), but I'm not willing to invest any more time...

14 20yrs

grant

14 20yrs grant

Xilinx Virtex-4 BRAM-16 Simulation

Does anyone have a Virtex-4 BRAM16 simulation running? I have been trying for two days now to get a simulation to work...

13 20yrs

bradsmallridge

13 20yrs bradsmallridge

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