Field-Programmable Gate Arrays

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Migrating Project from Xilinx ISE 4.1 to 8.1?

Got a project from a consultant using ISE 4.1 but of course the latest download is 8.1. If it matters, target device is...
6 comments posted 20yrs
posted by midicad2001
6 comments posted 20yrs posted by midicad2001

BRAM/XMD strangeness?

I have a V2P chip and am using both PPCs. Each has its own PLB bus and each PLB bus is connected to a small dual-ported...
6 comments posted 20yrs
posted by joeylrios
6 comments posted 20yrs posted by joeylrios

Xilinx HW-SPAR3_CPLD-DK kit

Please let me know any Xilinx distributor from any European Union country in order to by the HW-SPAR3_CPLD-DK kit. Xili...
1 comments posted 20yrs
posted by castel-electronics
1 comments posted 20yrs posted by castel-electronics

ATA controller in fpga

I want to implement an ata controller in the fpga,the controller use the ultra dma mode to read and write datas,and I wa...
9 comments posted 20yrs
posted by bjzhangwn
9 comments posted 20yrs posted by bjzhangwn

NIOS II fmax on a Cyclone

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project co...
1 comments posted 20yrs
posted by alessandro.strazzero
1 comments posted 20yrs posted by alessandro.strazzero

problem with the SRAM

HI, All I have questions regarding a project i am currently working on. I have been assigned to develop an vga_controll...
1 comments posted 20yrs
posted by qingwang_1978
1 comments posted 20yrs posted by qingwang_1978

programming devices using other tools

Hi, I want to know if anybody has never programmed fpga or proms not using Impact or Quartus programmer but other (thir...
3 comments posted 20yrs
posted by bergnoli
3 comments posted 20yrs posted by bergnoli

New PCI extender

Hello everyone Just wanted to share some of my recent experience from switching to Amfeltec PCI extender from the one f...
2 comments posted 20yrs
posted by stev.lee2006
2 comments posted 20yrs posted by stev.lee2006

Mistake in Xilinx dsp-book.pdf?

Hello! While working with a MAC-FIR I came across an equation in Xilinx' DSP-book (http://www.xilinx.com/publications/b...
3 comments posted 20yrs
posted by usenet0106
3 comments posted 20yrs posted by usenet0106

Student Pricing Now on our Website

As a prelude to our new website going live there is now a webpage with outline details of our University Access Program...
3 comments posted 20yrs
posted by removethisthenleavejea
3 comments posted 20yrs posted by removethisthenleavejea

Any FPGA with programming info available?

No, I'm not talking which pins to toggle how fast and when, but is there any 600K+ gate (roughly) FPGA available which a...
4 comments posted 20yrs
posted by weingart
4 comments posted 20yrs posted by weingart

what happens in SDR-SDRAM if i exceed tRAS(max)

Hi all, There is a situtation in my controller when tRAS(max) is exceeded. My controller starts to read out from some r...
4 comments posted 20yrs
posted by subhasri.krishnan
4 comments posted 20yrs posted by subhasri.krishnan

how do I minimize the logic in this function?

I have an async function with six bits in and eight bits out (listed below). I need to minimize the logic usage (in a V...
10 comments posted 20yrs
posted by brannonking
10 comments posted 20yrs posted by brannonking

FPGA Altair Advice

I was working on a Macintosh clone project (a clone of the original 128k), but I'm not willing to invest any more time...
14 comments posted 20yrs
posted by grant
14 comments posted 20yrs posted by grant