what happens in SDR-SDRAM if i exceed tRAS(max)

Question

Hi all,There is a situtation in my controller when tRAS(max) is exceeded. Mycontroller starts to read out from some row but I am not sure exactlywhich one. Does anyone know what row will be opened under thissituation? ThanksSubhasri.K

PeteS · Accepted Answer

tRAS is defined as'ACTIVE to PRECHARGE command' in a typical Micron datasheet(As a row can maintain itself only so long before being refreshed (thepurpose of precharge being part of the refresh system), it can only beaccessed without a precharge for some maxima. If you exceed thatmaxima, you will not change the row, you will simply get invalid data.Bottom line is - meet the tRAS spec.Note that the datasheet I mention above has full simulation modelsfreely available at the Micron website:Verilog, VHDL, IBIS, HSPICE, Denali and Synopsis are all available.CheersPeteS

Peter Alfke · Answer

Subhasri,you should of course always design according to the worst-case rules.But you should also know what's behind them.The refresh rate is dictated bythe leakage current that might drainenough charge away from (or add charge to) a storage capacitor to makethe stored bit invalid. The longer you wait, the more there is a chanceto have a bit (or many bits) flip.But leakage current is a strong function of temperature. At atemperature below the specified worst-case number (is that 70 or 85degrees C?) it will take longer to flip a bit. Leakage current doublesfor every 10 degrees. That means, at 10 degrees lower temperature, youcan, most likely, double the time between refreshes. But nothing isguaranteed...I do not advocate sloppy design, but it helps to know "the enemy".Peter Alfke, Xilinx, from home.===================================Subhasri krishnan wrote:

Peter Alfke · Answer

Subhasri,you should of course always design according to the worst-case rules.But you should also know what's behind them.The refresh rate is dictated by the leakage current that might drainenough charge away from (or add charge to) a storage capacitor to makethe stored bit invalid. The longer you wait, the more there is a chanceto have a bit (or many bits) flip.But leakage current is a strong function of temperature. At atemperature below the specified worst-case number (is that 70 or 85degrees C?) it will take longer to flip a bit. Leakage current doublesfor every 10 degrees. That means, at 10 degrees lower temperature, youcan, most likely, double the time between refreshes. But nothing isguaranteed...I do not advocate sloppy design, but it helps to know "the enemy".Peter Alfke, Xilinx, from home.===================================Subhasri krishnan wrote:

Subhasri krishnan · Answer

Thanks for the ideas both of you.

what happens in SDR-SDRAM if i exceed tRAS(max)

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