Mistake in Xilinx dsp-book.pdf?

Question

Hello!While working with a MAC-FIR I came across an equation in Xilinx'DSP-book ( seems to be wrong in my eyes.On page 65 equation 4.4 for the generic saturation level saysOutput width = ceil(log2(2^(b-1)*2^(c-1)*N))+1Where b/c are the numbers of data/coefficient bits and N is the filterlength.This formula is, apart from a missing parenthesis, ok, but the next onefor known coefficients saysOutput width = ceil(log2(2^(b-1)*abs(sum(coef))*N))+1Again missing right parenthesis and the N is in my eyes wrong, becauseit is already included in the sum of coefficients. Could anyone approvethis? I have to cite this paper in a thesis in lack of another sourcefor this equation (though it seems to be obvious, but I have to be sure).Thanks,Holger

Brian Drummond · Accepted Answer

The coefficients can be both positive and negative, and (for a unity gain filter) will typically sum to 1, not N.

Incidentally, counting the parentheses, I make it 5x( and 5x) in the above equation; where is the missing one?

- Brian

Holger Blum · Answer

Hello Brian!Brian DrummI know. But this formula uses already scaled and quantized coefficients,so they sum up to a much higher number which then can be taken todetermine the actual width of the output signal (for a DC input signal).In my design I have achieved unity gain by scaling the coefficients foran integer number of used bits and picking the desired active bits fromthe full-precision output. I am new to DSP on FPGA, but I think, thatthis is the right way.I felt so free to correct these mistakes. In the .pdf you could see thewrong equation.Regards,Holger

Brian Drummond · Answer

If the "much higher number" happens to be a power of 2, this is normal - simply scale the result to unity by selecting bits (effectively a shift). It is equivalent to moving the location of the decimal point (actually binary point).

It sounds as though you understand the issues; if your simulations work, that confirms it.

- Brian

Mistake in Xilinx dsp-book.pdf?

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