Is there an easy to disable timing analysis between two unrelated clocks in ISE 7.1? I don't want to have to put in specific ignores for all of the paths. I know that there are no timing errors since one clock is only used to write the registers, and the other clock only uses the contents of the registers when they are stable. Something like ignore all analysis for CLKX to CLKY would be ideal.
Thanks,
Chris
TIMESPEC "TS_a_to_b" = FROM "clk_a" to "clk_b" TIG; TIMESPEC "TS_b_to_a" = FROM "clk_b" to "clk_a" TIG;
The TIG timespec basically means 'timing path ignore'. This should do the trick for you.
cheers, aaron
Exactly what I wanted. I didn't realize that it was OK to have a FROM/TO with just named clock nets. I tried it and it got rid of a slew of non-errors.
Thanks, Chris
Have something to add? Share your thoughts — no account required.
Ask the community — no account required