Field-Programmable Gate Arrays

EDK 8.1 ... delay

Hi, does anybody know when EDK 8.1 will be ready? I'm also trying to buy the licence of Chipscope 8.1 from Avnet, but I...

3 comments posted 20yrs

posted by francesco.poderico

3 comments posted 20yrs posted by francesco.poderico

XilNet server data streaming problem from PPC

Hi On a Virtex-II Pro I'm attempting to write a very simple TCP/IP server application running on the PPC. The goal is t...

4 comments posted 20yrs

posted by xjohbex

4 comments posted 20yrs posted by xjohbex

LogiBlox on Foundation 4.1 Error

Hello out there, here's still anyone who uses this !! over the last years I used Foundation 4.1, Top-Level is schematic...

0 comments posted 20yrs

posted by martin.hansel

0 comments posted 20yrs posted by martin.hansel

Impact 8.1 problems with non xilinx device in chain

simple JTAG Chain: Atmel-SAM7 ARM --> XC3S1500 --> XC9572XL attempt to configure FPGA with Impact, done not high config...

20 comments posted 20yrs

posted by antti

20 comments posted 20yrs posted by antti

C to FPGA Tools (Impulse C and others) and necessary trig IP

I have been presented with a c program to implement on an fpga. I am investigating the possible processes/tools I could...

8 comments posted 20yrs

posted by pete.hudson

8 comments posted 20yrs posted by pete.hudson

tristate to logic conversion

hi, for some devices xilinx ise offers an option to convert internal tristate buffers to equivalent logic. however, i c...

10 comments posted 20yrs

posted by dfroehli

10 comments posted 20yrs posted by dfroehli

Multichannel Opb Memory Controller question

Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the co...

9 comments posted 20yrs

posted by marc

9 comments posted 20yrs posted by marc

Xilinx OBUF attributes on Spartan3

Hi, I'm trying to learn the way to work with output buffers and other features of the XC3S1000FG456 installed on my Ana...

12 comments posted 20yrs

posted by marco

12 comments posted 20yrs posted by marco

Are the Xilinx pcores files not searchable?

Hi, all I know some files in the folder: C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl. But when I...

3 comments posted 20yrs

posted by agou.win

3 comments posted 20yrs posted by agou.win

PPC Memory Management

Hi I was wondering if I could get some help with a project I'm trying to get started, I'm trying to embed some C code i...

1 comments posted 20yrs

posted by godzillalad

1 comments posted 20yrs posted by godzillalad

Current to sink PROG_B low?

I have desingned a board with an Atmega128 and Spartan3, such that the Atmega128 configures the FPGA via the slave seri...

11 comments posted 20yrs

posted by yaj_n

11 comments posted 20yrs posted by yaj_n

So Xilinx, is XDL and related libraries an available open source interface?

So the question to Xilinx is, will Xilinx release the NDA restrictions on XDL, and the associated library interfaces so...

43 comments posted 20yrs

posted by fpga_toys

43 comments posted 20yrs posted by fpga_toys

Microblaze data cache question

Hallo, I would insert multichannel opb sdram controller into a project. I would use xcl bus to access read/write datas...

5 comments posted 20yrs

posted by marc

5 comments posted 20yrs posted by marc

DDR2 SDRAM controller

I am writing veerilog code for DDR2 SDRAM controller using the micron memory module and I want to implement it on Virte...

7 comments posted 20yrs

posted by thisisandu

7 comments posted 20yrs posted by thisisandu

SDRAM Controller

I'm quite new to this area..I'm completeing a bachelor in electronics..As a part of my project i'm to create a sdram co...

4 comments posted 20yrs

posted by aravinthnm

4 comments posted 20yrs posted by aravinthnm