Field-Programmable Gate Arrays

Back to max thermal and power for XC4VLX200's

So, back to the question of worst case designs for supporting RC. What are the worst case VccInt currents that various...

35 comments posted 20yrs

posted by fpga_toys

35 comments posted 20yrs posted by fpga_toys

Wanted Help on All Digital PLL

I need material wchich cover all about ADPLL, which contains about operating principles and design (vlsi also). If there...

2 comments posted 20yrs

posted by neelagopi

2 comments posted 20yrs posted by neelagopi

Wanted Help on Aall Digital PLL

I need material wchich cover all about ADPLL, which contains about operating principles and design (vlsi also). If there...

0 comments posted 20yrs

posted by neelagopi

0 comments posted 20yrs posted by neelagopi

scrambling

Hi all, I need a VHDL source code scrambler/descrambler. Polyn : x ^ 7 + x ^ 6 + 1 I found some information on web (LFS...

2 comments posted 20yrs

posted by bhb22l

2 comments posted 20yrs posted by bhb22l

ERROR message when programming FPGA with Altium Designer 2004

Hi @ll, I'm new in FPGA Design. For my student research project I try to start running the Altium NanoBoard-NB1 with an...

5 comments posted 20yrs

posted by nils.hannemann

5 comments posted 20yrs posted by nils.hannemann

Constraining a 50 MSPS DAC Interface

Hello, I am trying to build an interface to a Analog Devices AD5447 digital analog converter on Xilinx Virtex-II 1000 a...

2 comments posted 20yrs

posted by derhagimann

2 comments posted 20yrs posted by derhagimann

URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM

Dears Altera provided USB Balster has no driver for Unix/HP-UX The current USB Blaster provided by ALTERA uses FTDI Chi...

3 comments posted 20yrs

posted by satishkmys

3 comments posted 20yrs posted by satishkmys

Interactive Logic software now available for download

Hello everyone. Hevday Logic's Interactive Logic software is now available for free download from http://www.hevday.com...

0 comments posted 20yrs

posted by andy.ward

0 comments posted 20yrs posted by andy.ward

a question: task, function vs module

Thanks for all that helped in my last problem about det FSM. As a beginner, I always meet this situation: When some sta...

0 comments posted 20yrs

posted by yyqonline

0 comments posted 20yrs posted by yyqonline

power up reset question

Hi, Background: Spartan 3 FPGA, Xilinx 6.3 tools I am currently having a problem with what I think is a power up reset....

2 comments posted 20yrs

posted by wolfendun1234-news

2 comments posted 20yrs posted by wolfendun1234-news

Analog FPGA Project -- VIdeo Router

I thought it might be a relatively fun and easy project to do a audio/video (coax or rca) matrix that can take any numb...

3 comments posted 20yrs

posted by benn686

3 comments posted 20yrs posted by benn686

Open source access to generate netlists into Altera tools? Others?

Ok, to be completely fair now that Xilinx clearly doesn't allow open source tools to generate net lists for the feature...

3 comments posted 20yrs

posted by fpga_toys

3 comments posted 20yrs posted by fpga_toys

Xilinx Legal

All: From our legal group- "Xilinx invests a significant amount in research and development, and vigorously protects an...

48 comments posted 20yrs

posted by austin

48 comments posted 20yrs posted by austin

TI Technical screening phone interview

Hey All, I have a technical screen interview with TI based in dallas. I am a front-end digital design engineer with two...

1 comments posted 20yrs

posted by saurster

1 comments posted 20yrs posted by saurster

Floating-Point Unit (for JOP)

Jidan Al-Eryani, one of my students, has implemented an FPU [1] which is now available for JOP. The FPU is connected vi...

0 comments posted 20yrs

posted by mschoebe

0 comments posted 20yrs posted by mschoebe