Hi all,
I need a VHDL source code scrambler/descrambler. Polyn : x ^ 7 + x ^ 6 + 1
I found some information on web (LFSR xilinx, etc...), but I have some problem with my example.
Thanks a lot for any reply about this subject (web, litteratur,vhdl code...). Brian
That's the SONET/SDH scrambler polynomial. I guess it could be also used in other applications. Data rates vary from 50-ish Mb/s to
40Gb/s. The rate will determine the sort of hardware implementation.Can you tell us a little more about your application? Things like data rate, bus width, clock rate, whether the scrambler needs to be reset (it does for SONET), whether the receiver has a self synchronising descrambler, etc.
Xilinx XAPP651 might give you some ideas.
Regards, Allan
...how many credit points it's worth...
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