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power up reset question

Hi,

Background: Spartan 3 FPGA, Xilinx 6.3 tools

I am currently having a problem with what I think is a power up reset. I have a fairly complicated design consistings of several state machines and a controller. I can get this to work easily by either downloading to the eeprom without powering off as well as simply downloading the bit file over jtag. However, when I power off and on the firmware no longer works. I know this particular board works with a much simpler version of this bit file, and has no problems with powering up.

Is the fact that my new design is more complicated allowing a power up reset problem to come into focus because the older versions of this were much simpler and not as prone to these types of problems? Is there some way to put a counter on the spartan 3 and do a global reset with it?

Tomorrow I think I will try to wire a hard reset onto the board but it is going to be a pain, I hope someone else might have encountered and solved a similar problem.

thanks, wolf

Reply to
Wolf
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When Xilinx FPGAs power up, internal logic and clock routing is gradually established as the configuration process proceeds. But all flip-flops are being held in a fixed state. At the end of configuration, this control signal ( often considered the "power-on reset") is released. Unfortunately, that control signal releases different parts of the chip at different times, since it has a total propagation delay that often is longer than a user-clock period. Different flip-flops or registers on the chip can thus become "alive" at different times, and when this difference occurs inside one state machine, an undesired sequence of operations might result.

It is wise to equip critical state machines with their own locally synchronously delayed release of the "power-on reset" condition, or to disable the Clock Enable input with a synchronous controller that has signal routing shorter than a clock period. Or you can suppress the clock until after the "power-on-reset" signal has gone inactive. Once you understand that the trailing edge of "power-on-reset" might have a delay difference or skew that exceeds a whole clock period, the solutions become obvious. This subject has been covered many times in this newsgroup. Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Wolf, are you sure is not the power supply? does the configuration process succeded? (done high?)

Aurash

Wolf wrote:

Reply to
Aurelian Lazarut

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