power up reset question

When Xilinx FPGAs power up, internal logic and clock routing is gradually established as the configuration process proceeds. But all flip-flops are being held in a fixed state. At the end of configuration, this control signal ( often considered the "power-on reset") is released. Unfortunately, that control signal releases different parts of the chip at different times, since it has a total propagation delay that often is longer than a user-clock period. Different flip-flops or registers on the chip can thus become "alive" at different times, and when this difference occurs inside one state machine, an undesired sequence of operations might result.

It is wise to equip critical state machines with their own locally synchronously delayed release of the "power-on reset" condition, or to disable the Clock Enable input with a synchronous controller that has signal routing shorter than a clock period. Or you can suppress the clock until after the "power-on-reset" signal has gone inactive. Once you understand that the trailing edge of "power-on-reset" might have a delay difference or skew that exceeds a whole clock period, the solutions become obvious. This subject has been covered many times in this newsgroup. Peter Alfke, Xilinx Applications

Wolf, are you sure is not the power supply? does the configuration process succeded? (done high?)

Aurash

Wolf wrote: