Field-Programmable Gate Arrays

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delay using integrator

I want to use the output of a R-C integrator as a delayed input to CPLD (inside there is a XOR gate and counter logic)....
1 comments posted 20yrs
posted by pradnya.karande
1 comments posted 20yrs posted by pradnya.karande

EDl Lab

For all of you that attended our seminars recently, and those that didn't, an updated version of the Raggedstone1 based...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

WebPACK license (and Quartus Web Edition too).

I'm Xilinx user, but interestingly to hear Altera users too. Everybody knows what WebPACK is free. How long does it fre...
8 comments posted 20yrs
posted by zlyh
8 comments posted 20yrs posted by zlyh

CPLD-SPI_flash configuration system problem.

I have a problem width my CPLD-SPI_flash configuration system. I have made a configuration interface for my Spartan 3 F...
3 comments posted 20yrs
posted by mughat
3 comments posted 20yrs posted by mughat

What is 1QN and 2QN in Xilinx CORDIC ?

Can someone please explain to me what the 1QN and 2QN formats are as used in the input and outputs of the Xilinx CORDIC...
1 comments posted 20yrs
posted by geewhiz1
1 comments posted 20yrs posted by geewhiz1

DIFF_OUT buffer example

Following up on John Providenza's question about the DIFF_OUT buffer feature, I've put together a small example which b...
11 comments posted 20yrs
posted by brimdavis
11 comments posted 20yrs posted by brimdavis

system generator : interrupt with FSL

Can i attach an interrupt to FSL perpherial under system generator? if so, how can i do?
0 comments posted 20yrs
posted by zhanghaobegin
0 comments posted 20yrs posted by zhanghaobegin

EDK Woes and Worries

Hey All, I am working on a relatively large design involving DSP on an FPGA. We use a Virtex4 LX60 and fill up about 50...
7 comments posted 20yrs
posted by Chris.Gammell
7 comments posted 20yrs posted by Chris.Gammell

DDR SDRAM on ML401

Has anybody managed to use the MiG to generate a controller for the DDR SDRAM on the Xilinx ML401 board? The RAM (infin...
0 comments posted 20yrs
posted by alastairlynch
0 comments posted 20yrs posted by alastairlynch

News from Embedded World in Nurnber

News from Embedded World News, Nurnberg 14.02.2006 Actel ===== Had no booth, but Actel-guy was moving around so I catch...
8 comments posted 20yrs
posted by Antti.Lukats
8 comments posted 20yrs posted by Antti.Lukats

can i use gcc of EDK?

Hi All, Iam working on a MPEG project for which Iam using the ML403 board. Iam new to this platfrom. My question is: Do...
1 comments posted 20yrs
posted by ramesh
1 comments posted 20yrs posted by ramesh

What is back_annotate?

Hi, Dears: I am using QuartusII now. I am not clear to back-annotate. What is back_annotate? and what's the use of back-...
4 comments posted 20yrs
posted by mailwz
4 comments posted 20yrs posted by mailwz

Xilinx EDK BRAM confusion

Hi all, I have 2 questions on different ways of using BRAM in EDK: 1. I have created a PPC system with DSOCM_BRAM and I...
4 comments posted 20yrs
posted by mbmsv
4 comments posted 20yrs posted by mbmsv