delay using integrator

I want to use the output of a R-C integrator as a delayed input to CPLD (inside there is a XOR gate and counter logic). It worked OK when I use discrete XOR IC 4070. But for same R-C values it doesn't works with CPLD. Is is due to the fact that analog input (sawtooth from integrator) has given to CPLD? Is comparator after integrator is one of the solution? Suggest other methods for creating delays inside CPLD. That will elliminate need of integrator. Here delay required is 1.1us.

Reply to
Sonali
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Yes. It probably only worked in the CMOS version because the parts are very slow as well as having a high threshold level. You should not normally provide slowly transitioning signals to digital logic unless the logic inputs have hysteresis (Schmitt triggers).

As long as the comparator has a fast enough edge rate for the CPLD.

This depends on your tolerance for delay jitter. For example if you had a 10 MHz clock you could use a shift register to delay 1.1uS +/- 0.1uS

Depending on the CPLD, you may have inputs with hysteresis that would work like your original CMOS circuit. The R-C values may need to change to make up for the difference in threshold voltage.

Reply to
Gabor

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