Field-Programmable Gate Arrays

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Need a SPI 4?

Hi I am working on 10 Gb Ethernet project. I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't kno yet...
1 comments posted 20yrs
posted by freechip
1 comments posted 20yrs posted by freechip

USB 2.0 OTG in FPGA

Hello, I'm trying to develop an USB 2.0 OTG interface with a FPGA (Xilinx or Altera). Therefore I think I'll have to ma...
5 comments posted 20yrs
posted by martinbosma
5 comments posted 20yrs posted by martinbosma

configuring Hardware

can any one please suggest ways of configuring FPGA/CPLDs with streaming data without using their IDE's . thnks
2 comments posted 20yrs
posted by abhishekbedi
2 comments posted 20yrs posted by abhishekbedi

Raggedstone1 - New Worldwide postage

The commonist question we have about Raggedstone1 is "have you got cheaper postage". So we have done something about it...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

Variables in VHDL and simulation

Hello, I have two some basic questions about the use of variables inside processes in VHDL and about the processes exec...
2 comments posted 20yrs
posted by frr
2 comments posted 20yrs posted by frr

using evaluated ip core with edk 7.1 i

Hi All... i'm quite new to EDK, I want to use the evaluated version of HDLC IP Cor with spartan 3 kit..can anyone sugge...
0 comments posted 20yrs
posted by akki_ani1
0 comments posted 20yrs posted by akki_ani1

From ASM to verilog Code

Hello: Does anyone know of any good examples showing the design flow from algorithm to ASM to coding of control and data...
0 comments posted 20yrs
posted by prasunp
0 comments posted 20yrs posted by prasunp

8051 IP core with JTAG debugger for FPGA?

Anybody here with experiences with syntetising some 8051 core with JTAG debugger in FPGA ? What core can you recommend ?
11 comments posted 20yrs
posted by Pszemol
11 comments posted 20yrs posted by Pszemol

Spartan3 decoupling

Hi, I'm making a board with a Spartan3 XC3S200, half of its pins available as I/O are yet occupied and I'd like to brin...
0 comments posted 20yrs
posted by marco
0 comments posted 20yrs posted by marco

High Speed Development Board

Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet whi...
1 comments posted 20yrs
posted by freechip
1 comments posted 20yrs posted by freechip

need byteblaster II source code

hi i am doing a project on altera fpga. i need to implement byteblaster in microcontroller so that i can configur fpga...
1 comments posted 20yrs
posted by chudar123
1 comments posted 20yrs posted by chudar123

project validation: best procedures?

Hi, We're trying to move our development and testing of VHDL code towards an automatic testing and validation system. H...
2 comments posted 20yrs
posted by Emanuel-Machado
2 comments posted 20yrs posted by Emanuel-Machado

altera max 7128s blanking

hello, I have max 7128s with blocked ISP. The ISP port is set off. How to erase eeprom without using special Altera APU...
3 comments posted 20yrs
posted by djanisz
3 comments posted 20yrs posted by djanisz