Variables in VHDL and simulation

Feb 23, 2006 2 Replies
F

Hello,



I have two some basic questions about the use of variables inside processes in VHDL and about the processes execution.



I would like to know if the variables will keep the last value each time a process is executed. During the simulation this is the normal behavior, however, I would like to know if the same will happen inside the FPGA device. I have read contradictory opinions about this topic on the Internet..



Also, I would like to confirm if when the FPGA starts all my processes will execute once and then each time an event occurs on any signal in their sensitivity list.



Thank you very much, Fabio



Vote
Twitter Facebook LinkedIn
M

Yes for variables declared in a process. No for variables declared in a procedure.

Yes. For example, see the waveforms here:

formatting link

Yes, in the sense that the synthesis netlist simulates the same as the process model. FPGAs contain gates and flops, not processes.

-- Mike Treseler

Vote
Twitter Facebook LinkedIn
B

It might be better to say that all processes are continuously executing all the time in an FPGA; the sensitivity list merely restricts the number of times they execute in simulation, to reduce simulation time.

For a combinational process, changing an input will result in appropriate output changes, even if the input is NOT in the sensitivity list

XOR:process(b) begin output

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required