ironic Xcell journal 1Q2006 cover art, S3E Starter Kit

Does anyone else find the cover art of the 1Q2006 Xilinx Xcell journal to be rather ironic, given how much Xilinx likes to trumpet their low power consumption compared to the other leading brand (e.g., Xilinx advertisement on page 28 of the same issue)?

I'm still eagerly awaiting the February 2006 availability of the Spartan-3E starter kit. Five more days to go, unless it slips again. Today if I click on the Spartan-3E Starter Kit in the online store, it takes me to a page declaring:

A technical problem has interrupted your session. We apologize for the inconvenience this has caused you.

Reply to
Eric Smith
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I got the technical problem some, too, but I didn't get it consistently. The link at the online store for the starter kit info ends in HW-SPAR3E-DK but should end in HW-SPAR3E-SK-US - make that change and you'll see there's now some documentation for the board! Wheeee!!!

Reply to
John_H

Well the boards do physically exist, Silica had one S3e SK board at Embedded, but the actual shipping is slipping to March, ASFAIK

Antti PS I did like page 3 on the Schematic! It takes one day to recover that missing schematic so why even bother hiding it?

Reply to
Antti

Maybe we should get an offering out there. Question is could we get the silicon as fast as we can make the board?

John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104Plus Spartan-3 Development Board.

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Reply to
John Adair

well 3 companies are known to be shipping s3e based boards for some time already, Xilinx seems to be simply delaying what is very strange as it really hard to belive that other companies are getting Xilinx silicon earlier than Xilinx himself!!

shipping are s3-100e based board from Avnet

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there are possible even more boards already shipping

Antti

Reply to
Antti

If we are going to do anything as a development board it won't be anything smaller than the XC3S500E. We are looking at cheap simple small modules for hobby use with smaller parts on but a few more boards to deliver before those appear. With 2 new development boards launching at DATE and planning an aggressive rollout of products for Q2 we have been somewhat busy.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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Reply to
John Adair

I had hopes of doing some wide LVDS testing (14-16 bit) using the S3E board when I first saw the schematics, given the new well-grounded expansion connector, and the soft-touch and unloaded terminators indicating some differential pair routing.

Unfortunately, after reviewing the {mirrored} gerbers and schematics, many of the "high speed" I/O connector signals are shared with other LED's and connectors, resulting in huge stubs on those lines, which are routed FPGA -> Hirose Connector -> other stuff, mostly on inner layers ( i.e. can't cut the stub off at the Hirose pad ).

There's maybe 7 unencumbered differential pair pins routed to the connector, of which four are input-only pins without LVDS output drivers.

Oh well; it's still a good value for the price, I just wish they'd manage to include provisions for high speed I/O one of these years.

Brian

Reply to
Brian Davis
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I'm a bit surprised that John Adair didn't reply to this.

Take a look at paged 13 and 14 of:

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ual_Issue_1_03.zip

It looks like their RaggedStone1 board should let you use

28 LVDS pairs quite easily. They indicate that they've routed the traces to minimize skew on those pairs too.
--
    Later,
    Jerry.

The universe is a figment of its own imagination.
Reply to
Jerry Coffin
[ ... ]

Oops -- that's 28 pairs per DIL, so the total's actually

56, not 28.
--
    Later,
    Jerry.

The universe is a figment of its own imagination.
Reply to
Jerry Coffin

I think that's a Spartan3 board, not a 3E

Also, the RaggedStone1 headers have 60 pins, one power, one ground

If everything's perfectly balanced, that pinout might be OK with low speed differential drivers, but I wouldn't try running any 640 Mbps data through it.

Brian

Reply to
Brian Davis
[ ... ]

Yes, that's correct. At least according to Xilinx, the basic difference between 3 and 3E is that the former emphasizes I/O while the latter emphasizes gates. As such, insisting that something be 3E based, but then complaining that only big/expensive ones have as many I/Os as you want doesn't seem to make a lot of sense.

You've mentioned better grounding in another post, so presumably that's what you see as being wrong here. Given that this is differential signalling, I'm not sure how the number of ground pins would mean much though. When you're doing single-ended signalling, you use lots of ground pins to maintain a stable ground plane, and you need to do that because your signal wires are referenced to ground. With differential signalling, the ground is necessary to complete the circuit, but the signals are referenced to each other, not to ground.

--
    Later,
    Jerry.

The universe is a figment of its own imagination.
Reply to
Jerry Coffin

It makes perfect sense that someone looking to test the new Spartan-3E I/O's would want to use a S3E, not an S3

Spartan-3E's have internal _DT terminators; Spartan-3's don't

Page 54 of the following also notes significant improvements in the I/O driver structure

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My specific complaint was that many of the expansion connectors, even on the vendor-sponsored eval boards, remain frighteningly sparse of grounds, well into the era of sub-ns I/O speeds.

When a few cents more to add a row of ground pins, route the I/O lines over a continuous ground plane, and not share the "high speed" I/O lines with on-board LEDs and such would be quite simple to implement.

If the signals were perfectly balanced and the PCB pairs

100% coupled entirely to each other rather than the ground plane, you could live with a ground-free I/O connector.

In practice, with real world PCB routes and drivers, maintaining ground return continuity through the expansion connector is important even for differential signalling at high speeds.

There was a nice thread on this over here:

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Brian

Reply to
Brian Davis

One thing I missed on the first read of the RaggedStone1 manual, is that seven pins of the middle LHS connector row can be selectively jumper grounded; this would let you get 3-4 LVDS pairs with nearby grounds.

Another nice provision is for DCI on the I/O banks, so you can use the various DCI terminations with the I/O connectors.

Maybe a future S3E board will have a G+-G connector pinout :)

Brian

Reply to
Brian Davis

Yes, that would certainly be true.

I can't say a lot for certain yet, but I'm supposed to be getting one of these sometime fairly soon, and I'm hoping to use some differential I/O. OTOH, it sounds like you're mostly interested in differential output, where I'll be using mostly differential inputs. If it comes to that, the 4 signals or so with (optional) nearby grounds will (barely) handle what I need for differential inputs, so I think it'll probably work for what I need in any case, but my first attempt will probably be without adding grounds.

Of course, it will probably also help that this will only be at 400 MHz...

--
    Later,
    Jerry.

The universe is a figment of its own imagination.
Reply to
Jerry Coffin

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