Field-Programmable Gate Arrays

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Nios2 and Shared Bus Resources

On a project I am working on, I recently had the requirement of embedding an ethernet controller into the system. Since...
0 comments posted 20yrs
posted by no_spam_me2
0 comments posted 20yrs posted by no_spam_me2

FIFO Simulation Oddities!

In my design I have one Asynchronous FIFO v6.1 that I instantiate twice. When I simulate my design (using Modelsim v 6....
9 comments posted 20yrs
posted by simon.stockton
9 comments posted 20yrs posted by simon.stockton

Virtex-4 DCM CLKFX jitter

The data sheet refers you to the Xilinx web site, but I can't find anything there for Virtex-4. Does the Virtex-II CLKFX...
2 comments posted 20yrs
posted by rsefton
2 comments posted 20yrs posted by rsefton

New Sydney-X2 FPGA development system

Hi all, The Sydney-X2 FPGA development system for education and FPGA computer application development has now been rele...
0 comments posted 20yrs
posted by tony
0 comments posted 20yrs posted by tony

Altera PowerPlay Analyser

Hi, I have a design with two identical 16 taps filters runing in parallel on the same inputs. A switch allow to disable...
1 comments posted 20yrs
posted by ag
1 comments posted 20yrs posted by ag

DDR for Spartan 3

Hi I would like to design a DDR controller for a Spartan 3. I have trie using MIG 1.5 but without much success. It clai...
0 comments posted 20yrs
posted by maxascent
0 comments posted 20yrs posted by maxascent

delay in altera cyclone about led

Dear all i write a simple test for led on altera cyclone board by jtag protocol such as following: led[0] will shine wi...
5 comments posted 20yrs
posted by offname
5 comments posted 20yrs posted by offname

XST issue / Answer record does not help

I'm facing an issue using TextIO in initialising a ROM block in my design... Here's the code snippet with the issue ::...
0 comments posted 20yrs
posted by satpreetsingh
0 comments posted 20yrs posted by satpreetsingh

Inferring RAM from array of records

A coworker asked me if I knew of a problem with synthesis tools inferring RAM (Xilinx is the target) from an array of r...
0 comments posted 20yrs
posted by wrightjt
0 comments posted 20yrs posted by wrightjt

Problem Solving Skills

Hello, I have been a software developer for the past 10 years now. I get job descriptions that requires problem-solving...
0 comments posted 20yrs
posted by bparanj
0 comments posted 20yrs posted by bparanj

need doc's for Insight Spartan II demo board

Greetings! Has anyone got machine readable, hence, net-transferable, documentation for the Insight Spartan-II demo boar...
1 comments posted 20yrs
posted by richard
1 comments posted 20yrs posted by richard