Field-Programmable Gate Arrays

FIFO Simulation Oddities!

In my design I have one Asynchronous FIFO v6.1 that I instantiate twice. When I simulate my design (using Modelsim v 6....

9 comments posted 20yrs

posted by simon.stockton

9 comments posted 20yrs posted by simon.stockton

Virtex-4 DCM CLKFX jitter

The data sheet refers you to the Xilinx web site, but I can't find anything there for Virtex-4. Does the Virtex-II CLKFX...

2 comments posted 20yrs

posted by rsefton

2 comments posted 20yrs posted by rsefton

New Sydney-X2 FPGA development system

Hi all, The Sydney-X2 FPGA development system for education and FPGA computer application development has now been rele...

0 comments posted 20yrs

posted by tony

0 comments posted 20yrs posted by tony

Altera PowerPlay Analyser

Hi, I have a design with two identical 16 taps filters runing in parallel on the same inputs. A switch allow to disable...

1 comments posted 20yrs

posted by ag

1 comments posted 20yrs posted by ag

a professional bus community and resource

www.buswares.com

0 comments posted 20yrs

posted by ted

0 comments posted 20yrs posted by ted

since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)

regards: since xilinx ise 8.1i support linux red hat 4.0 (with device Spartan-3 400k) After I install xilinx ise 8.1 un...

2 comments posted 20yrs

posted by mikelinyoho

2 comments posted 20yrs posted by mikelinyoho

slice macro replace the bus macro in the virtex-4 how to do that?????

hi everyone we know in the virtex-4 there haven't the bus macro so anyone know if we need the inter-connection between t...

12 comments posted 20yrs

posted by zhangxun0501

12 comments posted 20yrs posted by zhangxun0501

DDR for Spartan 3

Hi I would like to design a DDR controller for a Spartan 3. I have trie using MIG 1.5 but without much success. It clai...

0 comments posted 20yrs

posted by maxascent

0 comments posted 20yrs posted by maxascent

Troubles when upgrading Embedded Virtex-4Fx PowerPc

Hallo, I have a Virtex-4FX, and I have a design made with edk 7.1i. I have opened it into edk 8.1i and the applet asks...

1 comments posted 20yrs

posted by marc

1 comments posted 20yrs posted by marc

delay in altera cyclone about led

Dear all i write a simple test for led on altera cyclone board by jtag protocol such as following: led[0] will shine wi...

5 comments posted 20yrs

posted by offname

5 comments posted 20yrs posted by offname

XST issue / Answer record does not help

I'm facing an issue using TextIO in initialising a ROM block in my design... Here's the code snippet with the issue ::...

0 comments posted 20yrs

posted by satpreetsingh

0 comments posted 20yrs posted by satpreetsingh

Inferring RAM from array of records

A coworker asked me if I knew of a problem with synthesis tools inferring RAM (Xilinx is the target) from an array of r...

0 comments posted 20yrs

posted by wrightjt

0 comments posted 20yrs posted by wrightjt

Problem Solving Skills

Hello, I have been a software developer for the past 10 years now. I get job descriptions that requires problem-solving...

0 comments posted 20yrs

posted by bparanj

0 comments posted 20yrs posted by bparanj

need doc's for Insight Spartan II demo board

Greetings! Has anyone got machine readable, hence, net-transferable, documentation for the Insight Spartan-II demo boar...

1 comments posted 20yrs

posted by richard

1 comments posted 20yrs posted by richard

Shift Register synthesis??

Hi, while i was synthesizing a simple shift register i got an odd behavior. The device i'm using is a virtex2pro (xc2vp...

4 comments posted 20yrs

posted by giovannibusonera

4 comments posted 20yrs posted by giovannibusonera