DDS

You need a 48-bit accumulator, clocked at 200 MHz. Maybe you have to split it. Check the timing alculator for the ripple-carry delay. And remember that you will generate 5 ns of jitter, which widely overshadows your superb frequency resolution. Peter Alfke, Xilinx Applications.

A more recent Spartan family, yes.

How accurate do those 1uHz increments have to be? You can't get exactly 1uHz with a regular DDS. If your spec is

Well, from a 200MHz clock, you can get exactly 1uHz if you make the accummulator overflow at 200,000,000,000,000. i.e.

accum

Depends on your definition of "regular" DDS I suppose...

The logic to implement the pipelined mod 2e14 operation will probably be a lot harder than simply making a regular binary phase accumulator a few bits wider. Still, if the requirement is for a step size of

Regards, Allan

I am not too concerened about getting exactly 1uHz. I plan to use sine ramp, arb wave etc. I will use a external circuit with a comparator to ge a square wave.

cheers

Jon

The logic is extremely simple: When the MSbit changes, rather than adding PhaseInc add ((2^48)-(2e+14))/2+PhaseInc. The dual-increment value is very easy to support. I added the /2 in there for "whenever" the MSbit changes rather than just tracking the high-to-low transition.

Is the accuracy of your time base 1e-14? Calculate to 9 digits. Measure with a micrometer. Mark with chalk. Cut with an axe.

Are your specs really necessary?

I am not too concerened about getting exactly 1uHz. I plan to use sine ramp, arb wave etc. I will use a external circuit with a comparator to ge a square wave.

cheers

Jon

Not really I may alter them ;)

Jon

spec.

possible

Of course! I was thinking that the decision to add the extra (2^48-2e14) would have to take place prior to the register, but now I realise that it can be pipelined, which makes it possible to get it to run at 200MHz.

This may complicate downstream processing, e.g. use of CORDIC to generate a sinusoid.

Regards, Allan

Allan - why not use a down-counter and load it with 2e14, rather than doing a pipelined 2e14 decode?

It's not a counter, it's an accumulator. With a down counting accumulator, one would need to decode the underflow then load with

Besides, the OP stated that exact 1uHz resolution was not required, so it's cheaper and simpler to avoid decoding altogether and use the full

I agree with your sentiments though - it is sometimes eassier to implement a down counter than an up counter.

Regards, Allan

The thing I like most about this technique is that you can hit exact coarse decimal steps ( e.g. 1 kHz ) with a VERY short phase accumulator, enabling high precision lookups without any phase truncation.

Note that for sin lookup applications, you'll want to do the correction such that the phase bits off to the sine generation logic don't exceed your modulus on the correction cycle.

The earliest reference I've seen applying this technique to a sine output DDS is the Rockland/Wavetek decimal DDS patent: US Patent 3,735,269 Jackson 1973

Which is stamped on the back of my Wavetek 5130A, a classic direct analog mix-divide decade bucket architecture with the lower decade buckets replaced by the decimal DDS.

The neat thing about CORDIC's is that the units of angular measure can be whatever you want, and are not restricted to the classic 2*Pi Binary Angular Measure (BAM) encoding - just fix up the arctan table to match your desired units. With a short phase accumulator, it is also practical to pre-compute the rotation decisions and store them in a lookup table.

Thanks to Ray for pointing that out to me a couple times when I was stuck on the notion of a BCD CORDIC; but it never quite sunk in until after I looked at implementing it.

Another useful trick is to preserve the top two or three bits of the accumulator as pure binary to do quadrant/octant folding of the sin/cos functions- often seen in the BCD DDS ASIC's of yore. ( or more bits if you want binary weighted phase modulation )

Brian