Field-Programmable Gate Arrays

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Xilinx ISE tutorial revisited using MyHDL

Hi all: I have added a page to the MyHDL Cookbook, about a stopwatch design similar to the design from the Xilinx ISE t...
1 comments posted 20yrs
posted by jan
1 comments posted 20yrs posted by jan

XST takes unusually long

Hello All! We're working with a Xilinx Virtex II Pro board. As a part of our project, we had to write a hardware stack....
7 comments posted 20yrs
posted by dotnetters
7 comments posted 20yrs posted by dotnetters

false paths in Actel flow

Hello all, How do I set false-path constraints that follows the synthesis (Synplify 8.x) to PAR (Actel Designer) in Act...
1 comments posted 20yrs
posted by burn.sir
1 comments posted 20yrs posted by burn.sir

Problem with LwIP and MicroBlaze

I am trying to make a webserver on my ML401 development card and I use BSB to generate my hardware. When I try to "Gene...
6 comments posted 20yrs
posted by raybakk
6 comments posted 20yrs posted by raybakk

this JTAG thing is a joke

This post is a bit of a flame, but seriously, JTAG has got to go. The signals are weak. The various drivers and control...
27 comments posted 20yrs
posted by brannonking
27 comments posted 20yrs posted by brannonking

Xilinx RAM16_S9.V model syntax problem

I'm upgrading to ISE8.1 from ISE6.2 and my (old) Modelsim V5.5 is unhappy about some Verilog code in the Xilinx RAM16_S...
2 comments posted 20yrs
posted by johnp3+nospam
2 comments posted 20yrs posted by johnp3+nospam

Going from CLK1X to CLK2X.. really safe?

Got a DCM (spartan3), CLK1X coming CLK90 pin, thru a BUFG (to get 90deg out of phase from the incoming clk) CLK2X comin...
12 comments posted 20yrs
posted by mleikvol
12 comments posted 20yrs posted by mleikvol

Those yellow markers .... (ISE8.1)

OK, I surrender ! Any idea how I can clear those yellow markers that result from clicking on an error message, apart fro...
1 comments posted 20yrs
posted by dave.garnett
1 comments posted 20yrs posted by dave.garnett

regarding synopsys design anlyzer

Hi all, in the previous message i mentioned it as design compiler, but actually it is design analyzer. i am not sure wh...
1 comments posted 20yrs
posted by bachimanchi
1 comments posted 20yrs posted by bachimanchi

error from synopsys design compiler

Hi all, i am not sure whether i can post this message ,because this is regarding synopsys design compiler.After running...
0 comments posted 20yrs
posted by bachimanchi
0 comments posted 20yrs posted by bachimanchi

Lattice FPGA

Hi I was hoping to get some opinions on Lattice FPGAs compared to Xilinx an Altera. I see they have a SC device out. How...
24 comments posted 20yrs
posted by maxascent
24 comments posted 20yrs posted by maxascent