Despite trying all the read/write options on a Spartan 2 design I am moving to Spartan 3, The Spartan 3 BlockRAMS always seem to take one more clock to valid data output from a write from the other side.
I'm using ISE 6.3 and have tried inferring the RAMS with the VHDL source and using the core generator, no change.
Is there something fundamentally different between Spartan 2 and 3 blockRAMS timimg wise or is this a tool issue?
Pulling whats left of my hair out...
Peter Wallace
The Spartan3 BlockRAMs will do everything the Spartan2 does.
What changes with Spartan3 is the addition of write characteristics that allow "read first" and "no change" in addition to the Spartan2's "write first" mode. If all you're doing is reading, your results should be identical. Both Spartan2 and Spartan3 BlockRAMs have to register the input address to deliver the output data after the clock edge - neither are asynchronous memories.
Does your simulation suggest the data doesn't follow the address after the clock edge?
Data follows address in the expected way. What is different is how many clocks are required from write on port A to read of valid data at same address on port B. One more for Spartan3...
Peter Wallace
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