I'm upgrading to ISE8.1 from ISE6.2 and my (old) Modelsim V5.5 is unhappy about some Verilog code in the Xilinx RAM16_S9.V model (as well as some other of the RAM16 models).
The Xilinx model has two models built into it - a "legacy_model" and a new model. A `ifdef selects between them. In the newer model, there's some code that looks like:
reg [7:0] mem[2047:0];
for (count = 0; count < 32; count = count + 1) begin mem[count] = INIT_00[(count * 8) +: 8]; mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; // more lines like the above.
This is code straight from the Xilinx unisims directory.
Note the +: near the end of each line.
Is this legal Verilog? It looks illegal to me (and to Modelsim 5.5). It looks like an operator is missing. I don't believe Verilog allows this.
It also looks like the code couldn't possibly do the intended initialization.
Has anyone else run into this?
Thanks for any help!
John Providenza