false paths in Actel flow

Hello all,

How do I set false-path constraints that follows the synthesis (Synplify 8.x) to PAR (Actel Designer) in Actel Libero?

I have named all my false paths to xxx_falsepath, then created two SDC files with

define_false_path -to {{*_falsepath}} # for synplify

and

set_false_path -through {*_falsepath} # for designer

but none seem to work.

Ideally, i would like to set a single (or maybe two) attribute in the VHDL code and have it follow the design all the way down to PAR, is that at all possible?

regards,

-Burns