Hi all:
I have added a page to the MyHDL Cookbook, about a stopwatch design similar to the design from the Xilinx ISE tutorial:
The design is tackled in "the MyHDL way". The page describes the whole flow, including unit testing, automatic conversion to Verilog, and FPGA synthesis results.
MyHDL is a Python package that turns Python into a HDL.
Best regards,
Jan
Hi all:
I have added a page to the MyHDL Cookbook, about a stopwatch design similar to the design from the Xilinx ISE tutorial:
The design is tackled in "the MyHDL way". The page describes the whole flow, including unit testing, automatic conversion to Verilog, and FPGA synthesis results.
MyHDL is a Python package that turns Python into a HDL.
Best regards,
Jan
Have something to add? Share your thoughts — no account required.
Ask the community — no account required