Field-Programmable Gate Arrays

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FPGA : HSWAP

Hi I have a board with Spartan-3-e mounted on it. I am using HSWAP pin as an User I/O. I forgot to put an external pull...
1 comments posted 20yrs
posted by pbijoy
1 comments posted 20yrs posted by pbijoy

TNM propagation: I seem to be having trouble

Hi Folks, It's been a while since I've needed to do anything fancy with Xilinx timegroups, but I've inherited a design...
0 comments posted 20yrs
posted by john.l.smith
0 comments posted 20yrs posted by john.l.smith

Memory leaks with ISE 8.1

I have experenced memory leaks with the 8.1 release of the Xilinx tools on two different machines. I mean on the order o...
8 comments posted 20yrs
posted by dscolson
8 comments posted 20yrs posted by dscolson

Pacman update

At long last I have updated the Pacman release on www.fpgaarcade.com All ROMs are now internal, and RAMB16s are support...
0 comments posted 20yrs
posted by mikej
0 comments posted 20yrs posted by mikej

Xilinx hi-speed interconnect/routing question

I'm working on a V2Pro design that needs to have a small portion operate at over 400 MHz. As I've looked into the timin...
19 comments posted 20yrs
posted by johnp3+nospam
19 comments posted 20yrs posted by johnp3+nospam

Timing Diagram software recommendations?

When working on the low level design of FPGA modules I usually draw out a data path timing diagram showing what's happe...
1 comments posted 20yrs
posted by nial
1 comments posted 20yrs posted by nial

Digital filter design software?

Hello I?m wondering if there is any filter design software that can handle all required calculations in designing decima...
2 comments posted 20yrs
posted by bubb
2 comments posted 20yrs posted by bubb

Searching Dallas DS 2432 P or P+

Dear all, I am searching to buy Dallas DS 2432P or DS 2432P+. The DS 2432P is a 1kb Protected 1-Wire EEPROM with SHA-1...
1 comments posted 20yrs
posted by stephanie.berset
1 comments posted 20yrs posted by stephanie.berset

Number of taps for a FIR

Hello all, I am planning to introduce a decimation filter in my FPGA design in order to reduce the sample frequency by...
13 comments posted 20yrs
posted by rover8898
13 comments posted 20yrs posted by rover8898

Changes on xapp765 for ISE/EDK7.1 and 8.1?

Hello everyone! Any one knows if there are any (even minor) changes that have to be done to xapp765 to make it suitable...
0 comments posted 20yrs
posted by jeparra
0 comments posted 20yrs posted by jeparra

help on RISC controller developed mikej

now i have the complete correct code ( i got that from open cores.org) and i could pin point the errors im uploading th...
1 comments posted 20yrs
posted by selva991
1 comments posted 20yrs posted by selva991

FPGA : Spartan-3e configuration failure

Hi I have a board with Spartan-3e-100VQFP FPGA mounted on it. I am using SPI flash (M25p20 ) from ST, to store the conf...
4 comments posted 20yrs
posted by pbijoy
4 comments posted 20yrs posted by pbijoy

asynchronization FIFO in HDL co-simulation

my design using asynchronization FIFO simulated successfully in syste generator, but when i put the design's ngc file in...
0 comments posted 20yrs
posted by zhanghaobegin
0 comments posted 20yrs posted by zhanghaobegin