Memory leaks with ISE 8.1

Yes, I've seen thit too. It's not as bad since SP2, but its still there. I used to bitch about Quartus all of the time, since 8.x came out all I do is bitch about ISE.

Have you filed this with the hotline?

It really helps if when you catch it, you archive everything and send it in (if at all possible).

No one is perfect.

Software has bugs. Some more annoying than others. This sounds serious enough that someone would be put right on it.

Aust> Yes, I've seen thit too. It's not as bad since SP2, but its still

You don't need a project at all, just start ISE then close it 10 or so times. You'll notice that every time you do this the system has a bit less memory. I looked one day after using ISE my system was using

As far as entering a webcase, I've no energy to deal with Xilinx's tech support any more. Since Xmas I've entered 4 cases (not under this name in case you look). I had a very serious problem with BLVDS in a Spartan3E and it took me WEEKS just to get Xilinx to reproduce the problem. Most of my cases were sent to someone in China for support and that gives you about 1 email a day to work things out. My problem was 100% reproducible but it took them weeks to reproduce it because they did not have a Spartan3E board!!!

It is much less painful for me to re-boot my system every day when it starts to bog down than it is to go through another web case. My FAE knows of this and said he was going to enter a case on this soon. Last week I found a test bench generator bug that need to be looked into also. I would gladly go back to 7.1, but 7.1's bitgen screws up BLVDS for the Spartan3E, which is what I'm presently working on.

Sorry for the rant, but I'm a bit tender when Xilinx tech support comes up lately...

You don't need a project at all, just start ISE then close it 10 or so times. You'll notice that every time you do this the system has a bit less memory. I looked one day after using ISE my system was using

As far as entering a webcase, I've no energy to deal with Xilinx's tech support any more. Since Xmas I've entered 4 cases (not under this name in case you look). I had a very serious problem with BLVDS in a Spartan3E and it took me WEEKS just to get Xilinx to reproduce the problem. Most of my cases were sent to someone in China for support and that gives you about 1 email a day to work things out. My problem was 100% reproducible but it took them weeks to reproduce it because they did not have a Spartan3E board!!!

It is much less painful for me to re-boot my system every day when it starts to bog down than it is to go through another web case. My FAE knows of this and said he was going to enter a case on this soon. Last week I found a test bench generator bug that need to be looked into also. I would gladly go back to 7.1, but 7.1's bitgen screws up BLVDS for the Spartan3E, which is what I'm presently working on.

Sorry for the rant, but I'm a bit tender when Xilinx tech support comes up lately...

Not sure what that posted twice??? Sorry!

Neither ISE or Quartus are good environments for design entry or validation. I prefer a text editor and HDL simulator for that purpose. However, both ISE and Quartus do a credible job at synthesis and place+route if you start with known-good HDL files.

-- Mike Treseler

Hi Mike,

Quartus isn't a bad entry tool for HDL. It used to be until a few years ago, but the HDL parsing and synthesis have improved substantially. It gives you good error messages that locate you back to the offending bit of code. 3rd party synthesis tools offer a lot of value, but I wouldn't go so far as to say that you need "known-good HDL files" to use Quartus!

And Quartus doesn't leak any memory ;-)

Regards,

Paul Leventis Altera Corp.

I didn't say bad, I said not good for design entry. I guess I could spin that up to adequate for you. And outside of design entry it *is* good. Your static timing analyzer and RTL viewer are the best I've see for FPGAs.

My main knock against ISE and Quartus is that these tools foster dependence on vendor-specific wizards and core generators. I would like to see support at design entry for HDL inference of the same structures, and RTL instead of netlist based simulation.

-- Mike Treseler