Field-Programmable Gate Arrays

Modular Design and Incremental Design in ISE

Hi all, Is it possible to make Modular Design and Incremental Design flows parallelly? I explain: -If we have 3 modules...

0 comments posted 20yrs

posted by taileb.mehdi

0 comments posted 20yrs posted by taileb.mehdi

KEEP_HIERARCHY

I have a digital receiver module needed in a MicroBlaze system that I coded in Verilog. The module is responsible for a...

7 comments posted 20yrs

posted by mottoblatto

7 comments posted 20yrs posted by mottoblatto

Atmel microcontroller

Hi all, I have a question pertaining to an Atmel microcontroller. I have a AT89C2051 flash microcontroller. I just want...

4 comments posted 20yrs

posted by philip.hon

4 comments posted 20yrs posted by philip.hon

Concatenate String in Verilog?

Hi all, I want to open a lot of files and read data to reg. something like //-----code-------- $readmemh(".\pattern\0.d...

3 comments posted 20yrs

posted by zhushenli

3 comments posted 20yrs posted by zhushenli

Discrete

Can anybuddy tell me what are the most common methods of grabing discrete from out side world. These signals have no vai...

6 comments posted 20yrs

posted by faraz.khan

6 comments posted 20yrs posted by faraz.khan

Virtex II Pro

I would like to obtain a Virtex II Pro 20K part in FG676 package fo prototyping. I am in the UK and have seen the part...

1 comments posted 20yrs

posted by maxascent

1 comments posted 20yrs posted by maxascent

Testing sample Aurora design on ML321 board

Hi There, I've managed to compile a sample aurora protocol design using Coregenerator, and simulated it using ModelSim....

9 comments posted 20yrs

posted by bkamakot

9 comments posted 20yrs posted by bkamakot

Configuration pins on Spartan-3

I just had a design review on my board and I was zinged for using resistors to pull the M[2:0] pins to power or ground....

12 comments posted 20yrs

posted by spamgoeshere4

12 comments posted 20yrs posted by spamgoeshere4

ModelSim 6.0 missing Structure

In ModelSim 5.7 I would drag or right click items from a pane called Structure and drag them or add them to the Wave. Wh...

2 comments posted 20yrs

posted by bradsmallridge

2 comments posted 20yrs posted by bradsmallridge

FIFO Vs Shift Register

HI, Q1.What does FIFO depth mean. Q2.How can i use FIFO to register the signals comming out of FPGA. Q3.How would i add...

3 comments posted 20yrs

posted by faraz.khan

3 comments posted 20yrs posted by faraz.khan

Doubt about SERDES

Hello Groups, I have a 1Gbps SERDES output from the Network processor. But as i have 2 SERDES signal coming from the ba...

8 comments posted 20yrs

posted by praveenkumar.bm

8 comments posted 20yrs posted by praveenkumar.bm

ModelSim Designer

Anyone using this tool from Mentor? If so, any comments about it would be much appreciated. And any comments on how Mod...

10 comments posted 20yrs

posted by rsefton

10 comments posted 20yrs posted by rsefton

Spartan3E Phase-Shifter

I have some doubts about the SPT3E Phase Shifter. First: Data sheet V3.0, pg. 54, fig. 44: CLK180 is wrong. I must star...

2 comments posted 20yrs

posted by oen_no_spam

2 comments posted 20yrs posted by oen_no_spam

Xilinx Webpack vs Foundation ?

Hello all, What is the MAIN difference between Xilinx ISE Foundation and Xilinx ISE WebPACK ? Can they both do FPGA des...

4 comments posted 20yrs

posted by rover8898

4 comments posted 20yrs posted by rover8898

hwicap can be used in the virtex4

hi everyone! hwicap can be used in the virtex4 ? I try to use it but the EDK 7.1 tell me : error: MDT - opb_hwicap (opb...

12 comments posted 20yrs

posted by zhangxun0501

12 comments posted 20yrs posted by zhangxun0501