Testing sample Aurora design on ML321 board

Hi Billu,

The "Using High Speed Serial MGTs with the Aurora IP" Quickstart for the XUPV2P board at

does use Chipscope to monitor the data being sent and received over the Aurora link.

There is a Chipscope evaluation available for download at

Paul

billu wrote:

I would say, yes you should be concerned if the verify doesn't work. But if the board seems to be running okay... ?

Probably the simplest test is to monitor the channel_up signal out of the core. Your monitoring should verify that the signal is steady, too. If that is good, then the link is good and you should be able to send/receive data with no problem.

Hi There,

Thx for ur responses.

I'm assuming you'll need to write some HDL code to configure what transceivers you want to use and enable monitoring of the channel up, right? Is there any sample code available that does something like that. (dont have any experience w/ hdl). On that note, can the Aurora Bus functional model do something like that. I still cant completely understand what the bus functional model does.

- Bala

Duane Clark wrote:

Perhaps you need to discuss what it is you are trying to do, and in what context (homework, tinkering, work, ?).

As for an Aurora bus functional model; generally bus functional models are for simulation only. The Aurora core is simple enough that such a model is likely overkill, though I have never looked at one for the Aurora core (frankly, I did not know it existed).

For verify to work you need to configure bitgen to generate an extra file with bit masks. It is not generated by default.

/Mikhail

Hello,

Again, thx for everyones input

I'm trying to create a simple link/testbed for some frontends in our lab. One of the requirements for the protocol is to support framing/streaming interface. So as a starting point, I am trying to use the Aurora design core to demonstrate a link between 2 transceivers. I cant figure what to do once I have created the design core from Coregenerator. I would think, I have to integrate the Aurora core design w/ some HDL code that instructs the board to setup a link between 2 specific transceivers say MGT4 & MGT9, is that right. How can I monitor this link (is it possible to create an app similar to XAPP661 or something simpler) Is there any sample code that does something like this?

Thanks, Balaji

I think the bus functional model exists because Xilinx want Aurora to become a Standard, rather than just used by their FPGAs.

Colin

I guess part of the reason I asked that question is that you stated elsewhere "(dont have any experience w/ hdl)". This is a bit of a complex starter project.

There is no setting up of the link needed with the Aurora core. The core handles all this for you, and all you care about is getting a channel_up signal, which indicates the Aurora core is "finished" setting up the link. In your simulation, you should see this behavior, and that is just how the real hardware operates. If you don't get that, it is the first problem to fix.

For simple testing, I normally just implement a counter in the FPGA. Send that data out one end of the link, and test for the correct pattern at the receive side. I typically make the counter roll over at a non-power of 2 count. At the receive end, have a counter that counts errors.

How you get that information out depends on how much work you want to do, and what is available on the ML321 (I have not used that particular board). I like to use the PPC with an RS232 link to control the test and obtain results. But that can be a substantial amount of work by itself if you don't already have a working PPC system.

OK, so I finally figured out that you use PACE to assign I/O's of the Aurora design to the pins on the board. But, when I cant seem to try to assign the TX signals (TX_N or TX_P) to one of the MGT pins. (It color code is Brown and the legend says Gigabit serial)

XAP661 uses the PowerPC w/ an RS232 to control the test. Is it possible to just do some simple modifications and use that for testing? I guess I'll probably hold on to my other questions about testing until I get the basic design running.

Thx, Bala