Xilinx SelectMAP problem

Hi,

I have developed board with a Spartan 2E. The Spartan is configured by an antifuse fpga with the SelectMAP mode. The configuration of M[2:0] is ok. The configuration stream is transferred at 2.5MBytes/s. It said in the datasheet that the busy flag is provide for frequency above 50MHz. But in my design, I see a high level on the busy flag.

Somebody saw this kind of phenomena on Spartan 2E device? What was the origin of this phenomenon?

Thank you in advance

smu

Reply to
smu
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Hi smu,

usually this behavior is caused by incorrect data loaded into the device. The BUSY Signal will be driven high some CCLK cycles after the incorrect data has been loaded into the device. Have you checked the data alignment (D0=MSB), correct assertion/deassertion of CS#, and the setup/hold times on the select map interface?

Regards

Jens

smu schrieb:

Reply to
jenze

jenze a écrit :

Hallo Jens,

Where did you find this information?

This information could explain why it works in a previous version of my antifuse design. Probably some routing delay that made setup and hold time not conforms. I will check that.

Regards,

smu

Reply to
smu

Hi smu,

i have had similar problems some years ago on the Virtex-E. Virtex-E ist (nearly) the same as Spartan-2E. The BUSY Signal will be driven high if:

1) an abort has been requested. 2) the internal buffer is full. This will be the case if: 2a) CCLK is above 50 MHz 2b) the internal configuration packet processor is confused about the configuration data and stops interpretation. 3) the internal buffer is empty, and you try to readback configuration data. This is the case if: 3a) CCLK is above MHz 3b) switching from write to read, so the buffer need to be filled initially.

Regards

Jens

smu schrieb:

Reply to
jenze

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