I have some doubts about the SPT3E Phase Shifter.

First: Data sheet V3.0, pg. 54, fig. 44: CLK180 is wrong. I must start as high! (easy to see)

Data sheet V3.0, pg. 57, eq. 6: MAX_STEPS =

+/-[integer(20*(TCLKIN-3ns))] For example a 20MHz clock, TCLKIN=50ns MAX_STEPS = +/-[integer(20*47n)] = +/-[integer(940*10E-9)] = +/- 0Only seeing the "Answer Record: 22414" I understood. How about changing it to: MAX_STEPS =

+/-[integer(20***10E9***(TCLKIN-3ns))] ?

Now my doubts. What happens when we overflow the Phase Shifter? For the same 20MHz clock, MAX_STEPS = +/-940. And if I shift 941 times (same direction form zero) ?

*From the data sheet, PSCLK_FREQ (phase shift frequency input) ranges*

from 1MHz to 167MHz. For 1MHz: MAX_STEPS = +/-19940 There must be at least 19940 internal delay taps (for each side)! So I can go past 940 (the shifter doesn't know the frequency of the clock, I think).

Again the 20MHz clock. As MAX_STEPS = +/-940, the phase shift ranges from 940*20ps=18.8ns to

940***40ps=37.6ns, both below 50ns (TCLKIN). If 940 is the limit, how can the phase shifter, in the fixed mode, cover all the range from 0 to 2***pi (or 360 degrees, if you prefer)?

I want to know if there is a way of changing the phase continuously, crossing the borders of +/-2***N***pi smoothly (from 2*pi back to zero).

Luiz Carlos