To concatenate strings in Verilog, you can generally just use vector concatenation of the regs containing the string values. However, you should remain aware that it is not really a string concatenation, because that matters in some situations. For example, if you tried to do
reg [8*80:1] dir_name, file_name, full_name;
initial begin dir_name = "./mydir/"; file_name = "file.dat"; full_name = {dir_name, file_name}; $display("%s", full_name); end
This won't work, because file_name is not just "file.dat". It is "file.dat" with an extra 70 null or zero bytes in front of it. Those extra nulls will appear in the concatenation too. That 160 byte wide concatenation will get truncated back to 80 bytes when assigned to full_name, losing the part from dir_name entirely. But if you declared file_name to be 10 bytes, dir_name to be 70 bytes, and full_name to be
80 bytes, then everything would fit without any truncation.
Note that this also relies on the tools to ignore the embedded null characters in the full name when it is passed to a system task like $readmem, which some might not do.
Another way to build filenames with Verilog-2001 would be to use $swrite to print the filename, including numbers from loop counters, into a reg variable.