Field-Programmable Gate Arrays

SPI Problem

Hi all, I am trying to connect a device (DEI 1067) to Virtex4 FX and having problems to understand how to make this hap...

0 comments posted 20yrs

posted by fpgalearner

0 comments posted 20yrs posted by fpgalearner

New Computing/Electronics Forum - Please Join!

http://schoop.x.am Alerady has a few helpful, friendly members waiting to help you! Why not join and share your knowled...

0 comments posted 20yrs

posted by matt.hoy

0 comments posted 20yrs posted by matt.hoy

timing constraints ?

Hmmm.... Timing constraints ? Are *.ucf files created for a *typical* FPGA design ? I am designing an FPGA (xilinx spar...

4 comments posted 20yrs

posted by rover8898

4 comments posted 20yrs posted by rover8898

simulation of DCM blocks

Hi all, I am designing a hadware which use clk and 2xclk. I am planning to use DCm block in the V4 to get the 2x clock....

1 comments posted 20yrs

posted by vssumesh_asic

1 comments posted 20yrs posted by vssumesh_asic

FPGA : Chip-scope + spartan-3e

Hi I have a board with Spartan-3e with SPI-interface. i am using the JTAG interface to program the SPI-flash. all JTAG...

0 comments posted 20yrs

posted by pbijoy

0 comments posted 20yrs posted by pbijoy

xilinx XCVU2P-XC2VP30

Hi, In my design I want to use the compact flash interface to my processor in FPGA. In the development board ACE contro...

0 comments posted 20yrs

posted by prakash.na

0 comments posted 20yrs posted by prakash.na

To use adder and multiplier of DSP48 in V4

Hi all, Is it possible to use the adder and multiplier in the DSP48 block of the virtex4 FPGA separately but simultanio...

3 comments posted 20yrs

posted by vssumesh_asic

3 comments posted 20yrs posted by vssumesh_asic

want technical assistance in making toner chips

hi all i indent to make chips for toner cartridges ( specially hp ) in singapore i need technical assistance in this re...

4 comments posted 20yrs

posted by tonerchips

4 comments posted 20yrs posted by tonerchips

Area Constraints in Xilinx

Hi, Im somewhat new to the ISE and was wondering if there was a way to give the Xilinx tool an area constraint ( say in...

1 comments posted 20yrs

posted by ssirowy

1 comments posted 20yrs posted by ssirowy

very slow pull-up with CPLD design

We are using a Lattice LC4256V CPLD for a new design and we're having some problems with open drain outputs + 5V pullup...

2 comments posted 20yrs

posted by shawnn

2 comments posted 20yrs posted by shawnn

reading vhdl files

hi i am working on mp3 decoder in vhdl. i need to read the bitstream and decode it. the bitstream is in a file so i use...

1 comments posted 20yrs

posted by ace.shikha

1 comments posted 20yrs posted by ace.shikha

Simulating TFT core in EDK

I'm trying to use the TFT IP core provided by Xilinx and am unable to simulate the entire system using ModelSim 6.1e. I...

2 comments posted 20yrs

posted by jda59

2 comments posted 20yrs posted by jda59

Configuration Rate with multiple .bit files

All- I am combining 2 .bit files into one .mcs for an XCF16P (XC3S1500-676 and XC3S1000-456). In both cases I've set th...

6 comments posted 20yrs

posted by jbrower

6 comments posted 20yrs posted by jbrower

Interfacing to DDS v5.0 in System Generator

I have a system generator model that utilizes the DDS v4.1 block. I wish to upgrade to the DDS v5.0 block to take advan...

0 comments posted 20yrs

posted by ithorpe

0 comments posted 20yrs posted by ithorpe

Distributed Arithmetic

Hello everybody, am new to the group and have a question. Right now i am undergoing final semester training where my pr...

5 comments posted 20yrs

posted by nimayshah

5 comments posted 20yrs posted by nimayshah