simulation of DCM blocks

Hi all, I am designing a hadware which use clk and 2xclk. I am planning to use DCm block in the V4 to get the 2x clock. But the board is not yet available. So i thought to proceed with the post PAR test. Synthesized the a DCM block in which clk0 is fedback to clkfb through a bufg. generated post par simulation model using ISE 7.1. And simulated it on model sim with libraries X_DCM_ADV.v etc attached. But the clk0 and clk2x gives a flat '1' output not clock. Why is this behaviour. Is it possible to simulate the DCM behaviour ?? Sumesh V S