Field-Programmable Gate Arrays

NTSC video capture

Hello, I'm attempting to implement a hardware filter on an incoming video signal (either S-video or composite) using a...

1 comments posted 20yrs

posted by mfornero

1 comments posted 20yrs posted by mfornero

Very basic question

Hi, If i have a design based on system generator and i do not have any clock input to that do i still need clock input...

3 comments posted 20yrs

posted by fpgalearner

3 comments posted 20yrs posted by fpgalearner

code

Dear all First thanks for all give me help Second How check independence between row and column in low parity check mat...

0 comments posted 20yrs

posted by shereen.ahmed

0 comments posted 20yrs posted by shereen.ahmed

ROM resource sharing

Hello How to implement on-chip ROM memory resource sharing in FPGA? I implemented discrete cosine transform core using...

3 comments posted 20yrs

posted by mikel262

3 comments posted 20yrs posted by mikel262

location constraint doubt

In one of the ucf file I could see these. I could understand the logic element dll0 is constrained to be placed at DCM_...

1 comments posted 20yrs

posted by prakash.na

1 comments posted 20yrs posted by prakash.na

Register Map coding style

Hi, What is the best way to code a register map in a SOC? We have something like 15 different cores that all have a bun...

0 comments posted 20yrs

posted by david.lamb

0 comments posted 20yrs posted by david.lamb

LDPC

Dear Any one have a resource explain in detail the Viterbi algorithm for linear block codes

1 comments posted 20yrs

posted by shereen.ahmed

1 comments posted 20yrs posted by shereen.ahmed

unused pins

I try to port processor in xilinx FPGA. The processor code does 've more inputs, outputs, buffers declared in entity. N...

3 comments posted 20yrs

posted by prakash.na

3 comments posted 20yrs posted by prakash.na

How to handle the high fanout

I implement the design using xilinx device, and one net has high fanout, so I duplicate the register, but it does not w...

3 comments posted 20yrs

posted by hitsx

3 comments posted 20yrs posted by hitsx

get the data from tranceiver

hi, I am using opencores MAC in XUPV2P board. RxClk,RxData[3:0] are not coming out of LXT972A. What are all the trancei...

0 comments posted 20yrs

posted by arunprasath.c

0 comments posted 20yrs posted by arunprasath.c

xilinx JTAG

Hi, Iam trying to download opensource processor in xilinx dev. board XUPV2P. I'm not using any of the features like (Po...

3 comments posted 20yrs

posted by prakash.na

3 comments posted 20yrs posted by prakash.na

8:1 MUX implementaion in XILINX and ALTERA

Hi all, I wanted to know how many CLB's does a 8:1 mux implementation take in a ALTERA and a XILINX device. I wanetd th...

3 comments posted 20yrs

posted by praveen.kantharajapura

3 comments posted 20yrs posted by praveen.kantharajapura

xilinx DCM Timing warning

Hi Iam trying to synthesize using syn. pro and P&R using ISE. Iam planning to use XIlinx-DCM and generate 66MHz (at whi...

2 comments posted 20yrs

posted by prakash.na

2 comments posted 20yrs posted by prakash.na

New FPGA Technology Reaches New Heights

Silicon Valley based - Neural Systems Corporation (NSC) has developed a technology called trainable digital logic (TDL)...

0 comments posted 20yrs

posted by bsmithtech

0 comments posted 20yrs posted by bsmithtech

Creating macros

Hi guys, have a question can any1 help me with building a macro????? i have a VHDL design and i have mapped, placed and...

0 comments posted 20yrs

posted by harissh77

0 comments posted 20yrs posted by harissh77