very slow pull-up with CPLD design

We are using a Lattice LC4256V CPLD for a new design and we're having some problems with open drain outputs + 5V pullups. We've debuged and removed items from the system to the point where we have the single CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K resistor to +5V.

We configured the pins to output a 4MHz square wave for testing. When we hook a scope up to the pins, we see that the voltage rises at a very slow rate at the high edge of the clock pulse and only makes it to about 2V before the falling edge takes the output low. When we remove the pullups and set the pins to normal 3.3V mode we get a clean square wave, it is only when using pullups that problems are created.

Any ideas on why the pullup is taking so long to bring the pin voltage to 5V? We have used 4.7K pullups with other FPGA / CPLD designs before in designs faster than 4 MHz without any problems. Doing the math, it seems the acting capacitence from the CPLD is something like 15uF to have the pullup rise so slowly. Am I doing something wrong here?

Reply to
Loading thread data ...

The maths is suspect if you get 15uF.

4MHz is 125ns H/L, and a 125 ns Tau, is 26pF/4K7

So, your symptoms indicate ~26pf system c : That is highish, but not outlandish. What else is this connected to : Loads, track etc ?

Simple solution is to lower the pullup...


Reply to
Jim Granville

I would suggest a 1K pullup.

Also, a conventional 10x passive scope probe can add 10 to 12pF of capacitance to the circuit. You should use a 10x active probe with less than 1pF of input capacitance to see what is going on.

Daniel Lang

Reply to
Daniel Lang

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.