Field-Programmable Gate Arrays

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How to connect FPGA and µC

Hello, I want to attach an FPGA to a micro controller and therefore I'm looking for methods how to do this. Is there mor...
3 comments posted 20yrs
posted by thomas.reinemann
3 comments posted 20yrs posted by thomas.reinemann

ow to connect FPGA and µC

Hello, I want to attach an FPGA to a micro controller and therefore I'm looking for methods how to do this. Is there mor...
1 comments posted 20yrs
posted by Thomas.Reinemann
1 comments posted 20yrs posted by Thomas.Reinemann

Quartus SignalTap and bus turn around

Quartus SignalTap (and ISE equivalent ChipScope) are a truly awesome tools, however I ran into something strange. As pa...
2 comments posted 20yrs
posted by foobar
2 comments posted 20yrs posted by foobar

Xilinx DCI resistor placement guidelines

Hi, I have been unable to find any info/guidelines for PCB placement of the DCI reference resistors. I.e. the resistors...
6 comments posted 20yrs
posted by andrew.newsgroup
6 comments posted 20yrs posted by andrew.newsgroup

comparison with integer

All- Inside an always block, I have to search a bitfield in an array of registers and note it's position in a table. So...
2 comments posted 20yrs
posted by jbrower
2 comments posted 20yrs posted by jbrower

FLASH memory VHDL controller

hi, please anybody can share a VHDL controller for a FLASH memory likeAm29DL640 : http://www.spansion.com/products/Am29...
0 comments posted 20yrs
posted by philippe.chagny**NO-SPAM**
0 comments posted 20yrs posted by philippe.chagny**NO-SPAM**

PLD610

does anyone have any information about this chip? I heard it mentioned in the same sentence as a 22v10 but I havent been...
13 comments posted 20yrs
posted by samiamSPAMTHIS
13 comments posted 20yrs posted by samiamSPAMTHIS

INFO: *.XDL file

Hi guys, Any 1 help me with info on *.XDL file, i know that this file a ASCII verison of the NCD file. can 1 tell me whe...
3 comments posted 20yrs
posted by harissh77
3 comments posted 20yrs posted by harissh77

Virtex II Pro Config

Hi I am looking at ways to configure a Virtex II Pro Device. I want to ad some Flash memory for use with the PPC Core a...
0 comments posted 20yrs
posted by maxascent
0 comments posted 20yrs posted by maxascent

How to apply timing constrains for large bus

Hi all, I am working on a model which is basically a four bit 50 to 1 mux. There is four such blocks. To save area i am...
3 comments posted 20yrs
posted by vssumesh_asic
3 comments posted 20yrs posted by vssumesh_asic

DCM Question

I have an embedded project (MicroBlaze) that is currently using external oscillator to drive a DCM. The clkfx output of...
0 comments posted 20yrs
posted by mottoblatto
0 comments posted 20yrs posted by mottoblatto

XST not inferring distributed RAM

All- I cannot seem to coax XST to infer a distributed RAM -- I believe it should find a simple, single-port, asynchrono...
2 comments posted 20yrs
posted by jbrower
2 comments posted 20yrs posted by jbrower

Boolean as port type

Hello all, I take one of the ports as type Boolean in a VHDL module using Xilinx ISE. The code synthesizes and would al...
0 comments posted 20yrs
posted by yaseenzaidi
0 comments posted 20yrs posted by yaseenzaidi