Latest threads in Field-Programmable Gate Arrays

Simulated Quartus II delays are much greater than measured

I working on a design that uses an altera APF10K10ATC144-3 device. I have discovered some unusual long delays in a conf...

5 20yrs

oopere

5 20yrs oopere

VERIFICATION AND TESTPLAN

hi masters. this faq is very helpful. i need help!!! i'am currently doing verification of the zdut made in VHDL. i need...

2 20yrs

abrar_ahmed_313

2 20yrs abrar_ahmed_313

Virtex 2 Config Times

We are looking at using SRAM FPGA's for first time and trying to get an approximate config time for say a XCV2P40 using...

2 20yrs

jerome_l_horowitz

2 20yrs jerome_l_horowitz

SPARTAN3E SK LCD

I have SPARTAN3E STARTER KIT and I'm uncomfortable with its LCD off-backlight. I would like to turn on it permanently....

1 20yrs

aan.woodz

1 20yrs aan.woodz

FPGA with ASIC FPU units

SRC are talking about the following characteristics for a field-programmable floating-point device that they intend to...

1 20yrs

robin.bruce

1 20yrs robin.bruce

How to get divider in CRC32 , while implementatinh it in VHDL?

I am working on MAC802.3 & not getting How to get divider in CRC32 ?

1 20yrs

shailbadwaik

1 20yrs shailbadwaik

How to avoid lossing channel bonding when using Rocket IO?

Hi I'm using RocketIO with 4 channels, but they would loss banding when the data flow becomes fast. What would result in...

7 20yrs

frogkinger908

7 20yrs frogkinger908

Smallest uClinux configuration

I am trying to get uClinux to run in under 2MB of RAM without flash and if possible to still have networking support. A...

1 20yrs

jerickson

1 20yrs jerickson

Opinions on Viva

Just ran across this today, really inexpensive... Wonder how it stacks up to the 'free' tools from xilinx? ( im not qua...

3 20yrs

ziggy

3 20yrs ziggy

Xilinx Virtex-4 OCM Usage Issues

Hello to the group! I've been struggling to get the Xilinx IOCM and DOCM modules working with the PPC405 in my current...

13 20yrs

charles.eddleston

13 20yrs charles.eddleston

XDL router info needed

hi ALL!! i have a small query, FPGA geeks help me plz... I have a question on the XDL report, i am acually trying to mo...

2 20yrs

potter.ieee

2 20yrs potter.ieee

vhdl cpu emulator (any interest?)

During the design of my latest FPGA, I wrote a vhdl cpu emulator. I would like to know if there is interest in the (ope...

3 20yrs

nkmlists

3 20yrs nkmlists

Max and Argmax across 1,000 unsigned 10-bit numbers

Hello, I recently requested advice as to performing bit-matrix multiplication on bit matrices (bitwise AND followed by...

0 20yrs

andrewfelch

0 20yrs andrewfelch

PLB communication

Hi all, I need desperate help in two areas: 1. Can i do CRC check while transmiting data from PLB master to PLB slave....

0 20yrs

fpgalearner

0 20yrs fpgalearner

Heating problem of the CPLD

Hello, I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, my cpld some times work and sometimes doe...

7 20yrs

conphiloso

7 20yrs conphiloso

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