Field-Programmable Gate Arrays

VERIFICATION AND TESTPLAN

hi masters. this faq is very helpful. i need help!!! i'am currently doing verification of the zdut made in VHDL. i need...

2 comments posted 20yrs

posted by abrar_ahmed_313

2 comments posted 20yrs posted by abrar_ahmed_313

Virtex 2 Config Times

We are looking at using SRAM FPGA's for first time and trying to get an approximate config time for say a XCV2P40 using...

2 comments posted 20yrs

posted by jerome_l_horowitz

2 comments posted 20yrs posted by jerome_l_horowitz

SPARTAN3E SK LCD

I have SPARTAN3E STARTER KIT and I'm uncomfortable with its LCD off-backlight. I would like to turn on it permanently....

1 comments posted 20yrs

posted by aan.woodz

1 comments posted 20yrs posted by aan.woodz

FPGA with ASIC FPU units

SRC are talking about the following characteristics for a field-programmable floating-point device that they intend to...

1 comments posted 20yrs

posted by robin.bruce

1 comments posted 20yrs posted by robin.bruce

How to get divider in CRC32 , while implementatinh it in VHDL?

I am working on MAC802.3 & not getting How to get divider in CRC32 ?

1 comments posted 20yrs

posted by shailbadwaik

1 comments posted 20yrs posted by shailbadwaik

How to avoid lossing channel bonding when using Rocket IO?

Hi I'm using RocketIO with 4 channels, but they would loss banding when the data flow becomes fast. What would result in...

7 comments posted 20yrs

posted by frogkinger908

7 comments posted 20yrs posted by frogkinger908

Smallest uClinux configuration

I am trying to get uClinux to run in under 2MB of RAM without flash and if possible to still have networking support. A...

1 comments posted 20yrs

posted by jerickson

1 comments posted 20yrs posted by jerickson

Opinions on Viva

Just ran across this today, really inexpensive... Wonder how it stacks up to the 'free' tools from xilinx? ( im not qua...

3 comments posted 20yrs

posted by ziggy

3 comments posted 20yrs posted by ziggy

Xilinx Virtex-4 OCM Usage Issues

Hello to the group! I've been struggling to get the Xilinx IOCM and DOCM modules working with the PPC405 in my current...

13 comments posted 20yrs

posted by charles.eddleston

13 comments posted 20yrs posted by charles.eddleston

XDL router info needed

hi ALL!! i have a small query, FPGA geeks help me plz... I have a question on the XDL report, i am acually trying to mo...

2 comments posted 20yrs

posted by potter.ieee

2 comments posted 20yrs posted by potter.ieee

vhdl cpu emulator (any interest?)

During the design of my latest FPGA, I wrote a vhdl cpu emulator. I would like to know if there is interest in the (ope...

3 comments posted 20yrs

posted by nkmlists

3 comments posted 20yrs posted by nkmlists

Max and Argmax across 1,000 unsigned 10-bit numbers

Hello, I recently requested advice as to performing bit-matrix multiplication on bit matrices (bitwise AND followed by...

0 comments posted 20yrs

posted by andrewfelch

0 comments posted 20yrs posted by andrewfelch

PLB communication

Hi all, I need desperate help in two areas: 1. Can i do CRC check while transmiting data from PLB master to PLB slave....

0 comments posted 20yrs

posted by fpgalearner

0 comments posted 20yrs posted by fpgalearner

Heating problem of the CPLD

Hello, I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, my cpld some times work and sometimes doe...

7 comments posted 20yrs

posted by conphiloso

7 comments posted 20yrs posted by conphiloso

Spartan 3 documentation confusing...

I still have not completely figured out the pull up resistors on the Spartan 3 chips. It would appear that the data she...

26 comments posted 20yrs

posted by spamgoeshere4

26 comments posted 20yrs posted by spamgoeshere4